Abstract: An image processing apparatus or camera system comprises an image sensor 1, a geometrical position calculation device 6 for performing predetermined correction of a distortion, a first address table 10 for storing information correlating an input side address based on the calculation results of the geometrical position calculation device 6 to an output side address as a reference, a sort unit 11 for sorting the output side addresses according to the input side addresses, a second address table 12 for storing information correlating the output side address to the sorted input side address as a reference, and an address matching device 13 for matching the input side address of input side image data DI with the input side address stored in the second address table 12 and outputting output side image data DO.

Abstract: An improved base for a NPN bipolar transistor. The base region is formed with Boron and Indium dopants for improved beta early voltage product and reduced base resistance.

Abstract: An apparatus for sensing an input current through an inductor includes an RC circuit connected in parallel with the inductor across first and second input pins of an integrated circuit. A voltage monitoring circuit monitors a first voltage at the first input pin of the integrated circuit and monitors a second voltage at the second input pin of the integrated circuit. An op-amp compares the first voltage with the second voltage and generates a control output responsive to the comparison. A current sink circuit responsive to the indication controls the first voltage to substantially equal the second voltage.

Abstract: An optical sensor, according to an embodiment of the present invention, includes a photodetector region and a plurality of slats over the photodetector region. In an embodiment, the slats are made of an opaque polymer material, such as an opaque photoresist. In an embodiment, the slats are angled relative to a surface of the photodetector region.

Abstract: A circuit can compensate for intra pair skew or mode conversion in a channel by applying a second or corrective mode conversion effect that counters the channel's mode conversion. The circuit can process the common mode signal with a frequency dependent filter prior to injection back into the differential mode. The circuit can implement the reverse mode conversion with passive circuits using integrated resistors and metal oxide semiconductor (MOS) switches. In certain embodiments, such actions can proceed effectively without necessarily consuming active power.

Abstract: An optoelectronic apparatus includes one or more packaged optoelectronic semiconductor devices (POSDs), each including one or more optoelectronic elements encapsulated by a light transmissive molding compound. Each POSD includes a top surface formed by a top surface of the light transmissive molding compound that encapsulates the one or more optoelectronic elements of the POSD. Each POSD also includes a bottom surface including electrical contacts for the one or more optoelectronic elements of the POSD. A peripheral surface extends between the top and bottom surfaces. A light reflective molding compound surrounds the peripheral surface of each POSD and forms a reflector cup for each POSD. The electrical contacts on the bottom surface of each POSD are exposed, and thus, are accessible for electrical connections to other circuitry. Where the optoelectronic apparatus includes a plurality of POSDs, the light reflective molding compound also connects neighboring POSDs to one another.

Abstract: An electronic system, a reduced-noise reference voltage platform for a voltage converter device, and a method of manufacture of a reduced-noise reference voltage platform for a voltage converter device are disclosed. For example, the reduced-noise reference voltage (e.g., ground) platform includes a first conductor unit, a second conductor unit, and an insulator unit interposed between a first surface of the first conductor unit and a first surface of the second conductor unit. The reduced-noise reference voltage platform also includes a phase terminal connected to the first conductor unit, and a reference voltage (e.g., ground) terminal connected to the second conductor unit, wherein a second surface of the second conductor unit forms a platform coupled to the reference voltage (e.g., ground).

Abstract: Light sensors including dielectric optical coatings to shape their spectral responses, and methods for fabricating such light sensors in a manner that accelerates lift-off processes and increases process margins, are described herein. In an embodiment, a light sensor includes a photodetector sensor region formed in a semiconductor substrate, a dielectric optical coating filter covering the photodetector sensor region, and dummy dielectric optical coating features beyond the photodetector sensor region, wherein the dummy dielectric optical features include one or more dummy corners, dummy islands and/or dummy rings. Alternatively, or additionally, the dielectric optical coating filter includes chamfered corners, which improves the thermal reliability of the dielectric optical coating.

Abstract: A modulator with balanced slope compensation including a control network, a slope compensation network, an offset network and an adjust network. The control network receives a feedback signal indicative of an output voltage and provides a loop control signal. The slope compensation network develops a slope compensation signal. The offset network determines a DC offset of the slope compensation signal. The adjust network combines the DC offset, the slope compensation signal and the loop control signal to provide a balanced slope compensated control signal. The DC offset may be determined as a peak of the slope compensation signal. The slope compensation signal may be developed based on the output voltage and a pulse control signal, in which the pulse control signal is developed using the balanced slope compensated control signal.

Abstract: A voltage regulator integrated circuit comprises a control circuit driving at least one power switch to provide a regulated voltage at an output of an inductor/capacitor (LC) circuit coupled to the at least one power switch; an error amplifier having a first input coupled to a feedback signal representative of the regulated output voltage and a second input coupled to a reference signal; and a compensation network coupled to an output of the error amplifier and configured to provide a compensation voltage. The compensation network includes at least one digitally programmable resistor array and at least one digitally programmable capacitor array. Each array provides a plurality of user selectable component values. The control circuit includes a pulse modulator configured to modulate an input voltage based on the compensation voltage.

Abstract: One embodiment is directed towards a packaged chip including a lead frame. At least one chip is mounted on the lead frame. At least one edge the lead frame has a solder flow impeding feature located thereon. The solder flow impeding feature includes an integral portion of the lead frame that extends in a first projection outward at an edge of the lead frame and parallel to an external surface of the lead frame. An internal surface of the first projection is aligned with an internal surface of the main portion of the lead frame. The solder flow impeding feature also includes a second projection that extends from an external side of the first projection in a direction generally perpendicular to the first projection.

Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.

Abstract: A DMT system for a half-duplex two-way link carries Internet protocol encoded video stream on a coaxial cable that also carries a baseband rendition of the same video stream. A plurality of downlink symbols modulated on a subband of subcarriers in a downlink signal are decoded. The symbols may carry data encoded on a subband using a constellation of QAM symbols assigned to the subband. Other subbands may be associated with different QAM constellations. Lower-order constellations of QAM symbols may be assigned to subbands that include higher-frequency subcarriers and higher-order constellations of QAM symbols may be assigned to subbands that include lower-frequency subcarriers. A block error correction decoder may be synchronized based on an identification of the first constellation of QAM symbols and information identifying boundaries between the plurality of downlink symbols.

Abstract: An optical sensor includes a driver, light detector and echo canceller. The driver is adapted to selectively drive a light source. The light detector is adapted to produce a detection signal indicative of an intensity of light detected by the light detector. The echo canceller is adapted to produce an echo cancellation signal that is combined with the detection signal produced by the light detector to produce an echo cancelled detection signal having a predetermined target magnitude (e.g., zero). The echo canceller includes a coefficient generator that is adapted to produce echo cancellation coefficients indicative of distance(s) to one or more objects, if any, within the sense region of the optical sensor. The optical sensor can also include a proximity detector adapted to detect distance(s) to one or more objects within the sense region of the optical sensor based on the echo cancellation coefficients generated by the coefficient generator.

Abstract: A signal filter and accompanying methods. In one embodiment, the filter includes a first mechanism for receiving a first signal. A second mechanism employs one or more modified representations of the first signal to cancel one or more frequency components of the first signal, yielding an output signal in response thereto. In a more specific embodiment, the first mechanism includes a splitter for receiving the first signal and splitting the first signal onto a first path and a second path. The second mechanism further includes one or more delay modules and one or more phase shifters in the first path and/or the second path. One or more controllable amplifiers are optionally included in the first path and/or the second path. The one or more delay modules, phase shifters, or amplifiers are responsive to one or more control signals from a controller. The controller is adapted to modify behavior of the second mechanism so that the filter is characterized by a desired frequency response.

Abstract: Packaged light detector semiconductor devices (PLDSDs), methods for manufacturing PLDSDs, and systems including a PLDSD are described herein. In an embodiment, a PLDSD includes a light detector die having a surface including an active photosensor region, and a non-imaging optical concentrator including an entrance aperture and an exit aperture axially aligned with one another and with the active photosensor region. A molding material forms the non-imaging optical concentrator and encapsulates at least a portion of the surface of the light detector die that extends beyond the exit aperture of the non-imaging optical concentrator. The non-imaging optical concentrator concentrates light from the entrance aperture toward the exit aperture and onto the active photosensor region.

Abstract: A buck/boost voltage regulator generates a regulated output voltage responsive to an input voltage and a plurality of control signals. The buck/boost voltage regulator includes a plurality of switching transistors responsive to the plurality of control signals. Control circuitry monitors the regulated output voltage and generates the plurality of control signals responsive thereto. The control circuitry controls the operation of the plurality of switching transistors to enable a charging phase in a first mode of operation, a pass through phase in a second mode of operation and a discharge phase in a third mode of operation within the buck/boost voltage regulator to eliminate occurrence of a four switch switching condition.

Abstract: A feedback control system, e.g. a voltage regulator, may include a control stage controlling an output stage that generates an output. The control stage may generate a control signal, e.g. a pulse-width modulated signal, having a duty-cycle and a switching frequency, and adjust the switching frequency when a present value of the duty-cycle differs from a most recent previous value of the duty-cycle, until the duty-cycle starts increasing, while also adjusting the duty-cycle according to the output. By adjusting the switching frequency, the (power) efficiency of the system may be optimized also regulating the output. The feedback system may also adjust the switching frequency according to an alternate algorithm to improve but not necessarily optimize the power efficiency by scaling a programmed frequency value using a scaling factor that is a function of a maximum duty-cycle value, a present frequency value, the programmed frequency value, and a minimum frequency value.

Abstract: An electronic circuit (EC) may include an integrated current-source with an output terminal that may couple to the output of a power converter (OPC) to draw current from the power converter. The EC may further include control circuitry for activating the integrated current-source and for effecting a ramping output voltage at the OPC, and begin current-sense calibration once the output voltage reaches a specified calibration voltage value (SCVV). The control circuitry may regulate the output voltage to the SCVV while current-sense calibration is being performed, to measure and store the resistance value of a current-sense element of the power regulator. With the current-sense calibration complete, the control circuitry may disable the integrated current-source, resume ramping the output voltage until it reaches a specified regulation value (SRVV), and regulate to the SRVV during normal operation. The SCVV is specified to be at least a magnitude lower than the SRVV.

Abstract: A controller for a switch mode regulator with discontinuous conduction mode (DCM) correction which includes a correction network and a modulator. The correction network detects a low load condition indicative of regulation error during DCM and asserts an adjust value indicative thereof. The modulator receives the adjust value and adjusts operation accordingly to improve regulation during DCM. The correction network receives or determines a regulation metric, such as periods between successive pulses of a pulse control signal, or a current sense signal indicative of load current, and compares the regulation metric with one or more thresholds for determining the level of adjustment. Adjustment may be made using one or more methods, such as adjusting pulse on-time, adjusting pulse off-time, adjusting frequency of operation, etc.