Abstract: In an embodiment, an apparatus, such as a power-supply controller, includes a generator and an adjuster. The generator is configured to provide a switching signal that causes a power supply to generate a regulated output signal, and the adjuster is configured to impart a condition to the power supply while the power supply is operating in a first mode, the condition being approximately equal to a condition that the power supply would have if the power supply were operating in a second mode. For example, such an apparatus may be able to reduce or eliminate a transient on a regulated output signal (e.g., a regulated output voltage) when a power supply transitions from a first operating mode, such as a pulse-frequency-modulation (PFM) mode, to a second operating mode, such as a pulse-width-modulation (PWM) mode.

Abstract: A controller, for use with an SMPS DC-DC converter, includes a PWM/PFM generator and a switch driver. The PWM/PFM generator simultaneously generates CTRLPWM and CTRLPFM signals in dependence on a CTRL signal. The switch driver generates a drive signal in dependence on both the CTRLPWM and CTRLPFM signals. The drive signal is used to control a power switch of the DC-DC converter. The CTRL signal is generated in dependence on a feedback signal indicative of an output voltage or current of the DC-DC converter. Regardless of the mode of the DC-DC converter, the CTRLPWM signal is used to control a peak current in an inductor of the DC-DC converter, and the CTRLPFM signal is used to control a switching frequency of the power switch. In certain embodiments, both the CTRLPFM and CTRLPWM signals are varied in dependence on the feedback signal when the DC-DC converter is in a PWM-PFM mode.

Abstract: An equivalent series inductance (ESL) cancel circuit for a regulator for adjusting a feedback voltage by attenuating a magnitude of a square wave ripple voltage developed on an output voltage. The regulator includes an output inductor and an output capacitor, in which the capacitor has an ESL which forms an inductive voltage divider with the output inductor causing the square wave voltage ripple. The ESL cancel circuit may include first and second current sources and a resistor device coupled between the output node and an adjust node which is further coupled to a feedback input of the regulator. The first current source applies a current proportional to the output voltage to the adjust node. The second current source selectively applies a current proportional to the input voltage of the regulator based on a state of the pulse control signal.

Abstract: A system and method capable of injection locking the phases of a peak-valley multiphase regulator includes comparing an output voltage error signal with a ramp control signal and providing a corresponding slope reset signal, using transitions of the slope reset signal to develop a equally spaced high side ramp signals and equally spaced low side ramp signals, and injecting a corresponding one of the high side signals and a corresponding one of the low side ramp signals into each of the phases which correspondingly develop equally spaced pulse control signals for multiphase operation. Such injection locking allows the additional phases to operate out of phase with the first phase and allows operation at high duty cycles.

Abstract: Embodiments described herein relate to a method of manufacturing a packaged circuit having a solder flow-impeding plug on a lead frame. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch forming a trench. A non-conductive material that is adhesive to the lead frame is applied in the trench, such that the non-conductive material extends across the trench to form the solder flow-impeding plug. One or more components are attached to the internal surface of the lead frame and encapsulated. An external surface of the lead frame is etched at the dividing lines to disconnect different sections of lead frame as a second partial etch.

Abstract: Systems and methods for providing a full fail-safe capability in signal transmission networks are disclosed. For example, a system for providing a full fail-safe capability in signal transmission networks includes at least a first electronic circuit to transmit and receive signals or data, at least one driver unit coupled to the at least a first electronic circuit, and at least one receiver unit coupled to the at least a first electronic circuit and the at least one driver unit. The at least one receiver unit includes at least one offset signal generating unit, a signal comparing unit, and a switching unit to couple an offset signal from the at least one offset signal generating unit to an input of the signal comparing unit.

Abstract: Examples disclosed herein provide daisy chain communication system. The daisy chain communication system includes a plurality of transceivers coupled to devices which provide data signals to, and receive data signals from, their one or more coupled transceivers. The transceivers are configured to transmit and receive an amplitude modulated signal having edges corresponding to edges of a clock signal and amplitudes corresponding to a digital value of the first data signal.

Abstract: A device having a detector includes a sensor package. The sensor package includes a light sensor, at least one filter located over the light sensor and at least one bond pad. The light sensor is formed on a semiconductor device that provides sensor information related to light incident upon the light sensor. A perimeter of each bond pad is covered by a protective layer forming a sidewall seal. The sensor package also includes a package that encases the light sensor, filter(s) and bond pad(s). Additionally, at least one package pin is communicatively coupled to the bond pad(s). The device also includes a functional circuit that is coupled to the sensor package and receives the sensor information from the light sensor. The device can be an ambient light sensor, camera, backlit mirror, handheld electronic device, filter device, light-to-digital output sensor, gain selection device, proximity sensor, or light-to-voltage non-linear converter.

Abstract: A power converter comprises an input port configured to receive a source of power, an output port configured to provide output power, and a bridge circuit coupled to the input port. The bridge circuit comprises a first switch coupled in series with a second switch, and a third switch coupled in series with a fourth switch. A first clamp rectifier is coupled in series with a second clamp rectifier, and the first and second clamp rectifiers are coupled in parallel with the first and second switches. A first clamp capacitor is coupled between the first and second clamp rectifiers, with the first clamp capacitor operative to reduce power loss in the first and second clamp rectifiers. A first resonant inductor is coupled between the first and second switches. The power converter also includes a transformer operatively coupled to the bridge circuit, with the transformer comprising a primary winding and at least one secondary winding.

Abstract: An embodiment of a power supply includes an input node operable to receive an input voltage, an output node operable to provide a regulated output voltage, an odd number of magnetically coupled phase paths each coupled between the input and output nodes, and a first magnetically uncoupled phase path coupled between the input and output nodes. Such a power supply may improve its efficiency by activating different combinations of the coupled and uncoupled phase paths depending on the load conditions. For example, the power supply may activate only an uncoupled phase path during light-load conditions, may activate only coupled phase paths during moderate-load conditions, and may activate both coupled and uncoupled phase paths during heavy-load conditions and during a step-up load transient.

Abstract: An optical sensor, according to an embodiment of the present invention, includes a photodetector region and a plurality of slats over the photodetector region. In an embodiment, the slats are made up of a plurality of metal layers connected in a stacked configuration with a plurality of metal columns. The metal columns can be made of metal vias, metal contacts and/or metal plugs. In an embodiment, the slats are angled relative to a surface of the photodetector region, wherein the angling of the slats is achieved by the metal layers being laterally offset relative to one another and/or metal columns being laterally offset relative to one another. In an alternative embodiment, the slats are made of an opaque polymer material, such as an opaque photoresist.

Abstract: Embodiments of a leadframe for a device packaging are used not only for structural support and connectivity to the I/O pins to the external world, but also for housing and/or mounting devices above and below the leadframe. Being electrically conductive, the leadframe also serves as a low resistance interconnect and good current carrier between the bondpads on one device or between the bondpads on different devices above and/or below the leadframe.

Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Abstract: A packaged semiconductor device includes at least first and second lead-fingers. A molded structure forms a cavity and is molded around portions of each of the first and second lead-fingers to thereby mechanically attach each of the first and second lead-fingers to the molded structure. A semiconductor structure (e.g., a IC, chip or die) is attached within the cavity. First and second bond wires respectively providing electrical connections between the semiconductor structure and the first and second lead-fingers. A further portion of each of the first and second lead-fingers is mechanically attached to a bottom surface of the semiconductor structure to inhibit relative mechanical motion between the semiconductor structure, the molded structure and the first and second lead-fingers.

Abstract: A semiconductor structure for enhanced ESD protection is disclosed. The semiconductor structure includes a plurality of fingers, wherein each finger of the plurality of fingers includes a plurality of voltage clamps, and each voltage clamp of the plurality of voltage clamps includes at least a first well having a first conductivity type and a second well having a second conductivity type, and a connection between a well tie of the first well of a first voltage clamp of the plurality of voltage clamps and a well tie of the first well of a second voltage clamp of the plurality of voltage clamps, wherein the connection is enabled to couple a bias voltage associated with a current flow in the first voltage clamp to the second voltage clamp, and the first voltage clamp and the second voltage clamp are thereby enabled to trigger on substantially simultaneously.

Abstract: A novel integrated switched mode power supply circuit that provides supply voltages to an integrated circuit may be of minimal complexity and have the capacity for a wide range of input supply voltages. The novel power supply may include cascaded, unregulated step-down charge pumps (e.g. unregulated voltage splitters), one or more linear regulators coupled to the output of the cascaded voltage splitters, and a start-up current source to provide the IC supply current until the input supply voltage is sufficiently high for the voltage splitter(s) to be functional to provide the IC supply current. Furthermore, each voltage splitter may be activated or disabled depending on the value of the input supply voltage, and the input of a disabled voltage splitter may be shorted to its output via an integrated power switch. Using (cascaded) voltage splitters to provide the IC supply current reduces overall power dissipation in the IC.

Abstract: Methods, systems and devices described herein improve vertical resolution at sides of a four cornered image produced by a scanning projector display device. In accordance with an embodiment, a first plurality of frames (e.g., odd frames) of the image are scanned back and forth from side to side starting at a first line level, in one of the corners. Additionally, a second plurality of frames (e.g., even frames) of the image are scanned back and forth from side to side, starting at a vertical offset level from the first line level, in the same one of the corners. The scanning of the first plurality of frames (e.g., the odd frames) is interleaved with the scanning of the second plurality of frames (e.g., the even frames).

Abstract: An optoelectronics apparatus selectively drives a light source, and includes four electrically isolated photodetector (PD) segments that detect light that has reflected off an object. Each of the four PD segments produces a corresponding signal, referred to as signals A, B, C and D, indicative of the light detected by the respective PD segment. Circuitry is used to produce a first motion signal indicative of a sum of the signals A plus B minus a sum of the signals C plus D, i.e., the first motion signal is indicative of (A+B)?(C+D). Further circuitry produces a second motion signal indicative of (B+C)?(A+D). Additional circuitry produces a signal and/or data that is indicative of a direction and/or rate of motion of an object, in dependence on the first and second motion signals.

Abstract: An LED driver system including an input receiving a rectified AC conductive angle modulated voltage on a rectified node, a converter, a low-pass filter, and AC detector, and a driver network. The converter is coupled to the rectified node and includes a power switching device coupled to a switching node, in which the power switching device is controlled to convert the rectified AC conductive angle modulated voltage to an output voltage and output current. The low-pass filter is configured to filter voltage of the switching node to provide a filtered voltage. The AC detector receives the filtered voltage and provides a current sense signal indicative thereof. The driver network controls duty cycle of the power switching device based on the current sense signal.

Abstract: Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). In order to obtain an error measure for offset, gain or phase, errors, outputs from each ADC are either summed or averaged over No samples. Calling each of the sums or averages as Xk where k=1, 2, . . . , M, there are M such values as a result. A single value representing the mean of these M values, Xmean, is chosen as a reference value. The offset, gain and phase errors for the M different ADCs are then obtained from Xk?Xmean. The sign of each offset error, i.e., sign (Xk?Xmean), is then used to drive an adaptive algorithm whose output represents an offset correction value for the corresponding ADC. The offset, gain, and phase correction outputs from the adaptive algorithm is fed to an array of Digital-to-Analog converters (DACs) whose outputs are voltages or currents that directly or indirectly controls the offset, gain or phase setting of each individual ADC.