Abstract: A modulator for controlling a switch circuit of a voltage regulator, including a sense circuit that provides a current sense signal indicative of current through the output inductor, a ramp circuit that develops a ramp voltage on a ramp node using the current sense signal, an error circuit that develops an error signal indicative of output voltage error and that injects the error signal into the ramp node to adjust the ramp voltage, a comparator circuit that compares the ramp voltage with a fixed control voltage to develop a compare signal, and a logic circuit that uses the compare signal to develop a pulse control signal that controls the switch circuit. The output voltage error may be determined by comparing the output voltage with a reference voltage and converting the error voltage to a current applied to the ramp node.

Abstract: A controller, for use with an SMPS DC-DC converter, includes a PWM/PFM generator and a switch driver. The PWM/PFM generator simultaneously generates CTRLPWM and CTRLPFM signals in dependence on a CTRL signal. The switch driver generates a drive signal in dependence on both the CTRLPWM and CTRLPFM signals. The drive signal is used to control a power switch of the DC-DC converter. The CTRL signal is generated in dependence on a feedback signal indicative of an output voltage or current of the DC-DC converter. Regardless of the mode of the DC-DC converter, the CTRLPWM signal is used to control a peak current in an inductor of the DC-DC converter, and the CTRLPFM signal is used to control a switching frequency of the power switch. In certain embodiments, both the CTRLPFM and CTRLPWM signals are varied in dependence on the feedback signal when the DC-DC converter is in a PWM-PFM mode.

Abstract: A modulator configured to control switching of current through an inductor of a converter according to a current limiting scheme while converting an input voltage to an output voltage, which includes a current limit generator and a comparator network. The current limit generator is configured to provide a periodic ramping current limit value based on either the input voltage or the output voltage, an inductance of the inductor, a timing signal, and a predetermined maximum output current of the boost converter. The comparator network is configured to provide a switch control signal to control switching of current through the inductor by comparing a current sense value indicative of a current through the inductor with a lesser of a compensation error value and the periodic ramping current limit value. The converter may be configured as a peak current mode control converter in either boost or buck mode.

Abstract: Described herein are methods for fabricating a plurality of optoelectronic devices, and the optoelectronic devices resulting from such methods. One such method includes performing through silicon via (TSV) processing on a wafer, which includes a plurality of light detector sensor regions, to thereby form a plurality of vias, and then tenting and plating the vias and performing wafer back metallization. Thereafter, plurality of light source dies are attached to a top surface of the wafer, and a light transmissive material is then molded to encapsulate the light detector sensor regions and the light sensor dies therein. Additionally, opaque barriers including opaque optical crosstalk barriers are fabricated. Further, solder balls or other electrical connectors are attached to the bottom of the wafer. The wafer is eventually diced to separate the wafer into a plurality of optoelectronic devices.

Abstract: A regulator system with dynamic droop including a regulator control network which is adapted to control regulation of an output voltage to a reference level, a DC droop network which provides a droop signal to modify the reference level based on output load according to a predetermined DC load line, and a dynamic droop network which adjusts the droop signal to delay recovery to the predetermined DC load line within an AC load line tolerance in response to a load transient. A transient reduction network may be included to reduce transient overshoot for load insertion or release depending upon duty cycle type. The dynamic droop network adjusts the droop signal to optimize utilization of an AC delay parameter while transitioning between an AC offset voltage allowance and the predetermined DC load line.

Abstract: A remote differential voltage sensing circuit having a voltage input (Vin) and a voltage output (Vout), comprises a dual differential input stage including a common-source or common-collector differential input stage in parallel with a common-gate or common-base differential input stage. The common-source or collector differential input stage has differential inputs, one coupled to the voltage input (Vin) and the other coupled to the voltage output (Vout). The common-gate or common-base differential input stage has differential inputs, one coupled to a local ground (Agnd) and the other coupled to a remote ground (Rgnd). An output stage is driven by an output of the dual differential input stage and produces an output voltage at the voltage output (Vout). A compensation network is coupled between the voltage output (Vout) and the output of the dual differential input stage.

Abstract: Systems and methods for providing a full fail-safe capability in signal transmission networks are disclosed. For example, a system for providing a full fail-safe capability in signal transmission networks includes at least a first electronic circuit to transmit and receive signals or data, at least one driver unit coupled to the at least a first electronic circuit, and at least one receiver unit coupled to the at least a first electronic circuit and the at least one driver unit. The at least one receiver unit includes at least one offset signal generating unit, a signal comparing unit, and a switching unit to couple an offset signal from the at least one offset signal generating unit to an input of the signal comparing unit.

Abstract: An embodiment is an apparatus that includes an energy-storage circuit and a rectifying circuit. The energy-storage circuit is configured to generate a current that flows in a direction, and the rectifying circuit is configured to substantially block the current from flowing in a reverse direction in response to the current. Such an apparatus may be configured to block a reverse current before it begins to flow. For example, such an apparatus may include a transistor disposed in the path of the current, and may be configured to deactivate the transistor while a forward current is still flowing. Furthermore, by being configured to block the current from flowing in a reverse direction in response to the current itself, such an apparatus may better block a reverse current than an apparatus that blocks a reverse current in another manner, such as in response to a voltage across a rectifying transistor.

Abstract: A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the at least one trench, the electrically conductive material providing an electrical connection to the electrical device through the active layer.

Abstract: A voltage regulator integrated circuit comprises a control circuit driving at least one power switch to provide a regulated voltage at an output of an inductor/capacitor (LC) circuit coupled to the at least one power switch; an error amplifier having a first input coupled to a feedback signal representative of the regulated output voltage and a second input coupled to a reference signal; and a compensation network coupled to an output of the error amplifier and configured to provide a compensation voltage. The compensation network includes at least one digitally programmable resistor array and at least one digitally programmable capacitor array. Each array provides a plurality of user selectable component values. The control circuit includes a pulse modulator configured to modulate an input voltage based on the compensation voltage.

Abstract: Systems and methods for operating cameras are described. An image signal received from an image sensor can be processed as a plurality of video signals representative of the image signal. An encoder may combine baseband and digital video signals in an output signal for transmission over a cable. The video signals may include substantially isochronous baseband and digital video signals. The baseband video signal can comprise a standard definition analog video signal and the digital video signal may be frequency modulated before combining with the baseband video signal and/or transmitting wirelessly. The digital video signal may be a compressed high definition digital video signal. A decoder demodulates an upstream signal to obtain a control signal for controlling the position and orientation of the camera and content of the baseband and digital video signals.

Abstract: Described herein are optical proximity detectors, methods for use therewith, and systems including an optical proximity detector. Such optical proximity detectors include an analog front-end and a digital back-end. In certain embodiments, the digital back-end includes a dynamic gain and phase offset corrector, a cross-talk corrector, a phase and magnitude calculator, and a static phase offset corrector. The dynamic gain and phase offset corrector corrects for dynamic variations in gain and phase offset of the analog front-end due to changes in temperature and/or operating voltage levels. The crosstalk corrector corrects for electrical and/or optical crosstalk associated with the analog front-end. The phase and magnitude calculator calculates phase and magnitude values in dependence on the corrected versions of digital in-phase and quadrature-phase signals received from the analog front-end. The static phase offset corrector corrects for a static phase offset of the optical proximity detector.

Abstract: A sigma-delta converter may include a filter coupled to a first summation circuit and a second summation circuit. A multi bit quantizer may be coupled to the second summation circuit. A single bit digital-to-analog converter (DAC) may be included that defines a feedback path between the multi-bit quantizer and the first summation circuit. A feed-forward coefficient circuit defining a feed forward path between the first summation circuit and the second summation circuit may be included.

Abstract: A communications channel may radiate energy undesirably, for example in the form of electromagnetic radiation, when a communication signal transmits over the communications channel. Processing the signal before and after transmission on the communications channel can reduce the level of radiated energy. Signal processing in advance of transmission over the communications channel can transform the communication signal into a waveform that has a reduced propensity to emit radiated energy during transmission over the communications channel. Exemplary signal transformations can involve applying either frequency-selective or broadband attenuation to the communication signal. Following transmission of the waveform over the communications channel, the original communication signal can be restored via reversing the signal transformation. The reverse transformation can comprise applying frequency-selective gain or broadband gain to the transmitted waveform.

Abstract: Configuring the operational behavior of an integrated circuit. The integrated circuit (IC) comprises a plurality of configuration inputs for configuring the IC. The IC also has a memory which stores a plurality of sets of parameter values. Each parameter value of the respective set corresponds to a different operational parameter of a plurality of operational parameters. The IC includes logic which determines a first plurality of configuration values corresponding to the first plurality of configuration inputs. The logic then selects a set of parameter values from the stored plurality of sets of parameter values. The selection of parameter values is based on the first plurality of configuration values. The IC is then configured for operation according to one or more operational parameter values in the selected set of parameter values.

Abstract: An image communication system includes a coaxial cable having first and second ends. A monitor station is coupled to the first end and a camera is coupled to the second end. The monitor station provides power to the camera through the cable, while the cable is also used to carry communication signals transmitted by the camera to the monitor station. The image communication system includes a first active inductor coupled to the first end and a second active inductor coupled to the second end. A current-compensation circuit may also be provided.

Abstract: Voltage regulators in a current share arrangement may provide a total current to a common load, and may be simultaneously turned on to ramp up member currents. Each voltage regulator may provide a respective member current in the current share configuration. A target current value may be determined from a cycle-averaged current value of the member currents and a voltage error value of the voltage regulator, and each member current may be ramped to the target current value instead of the cycle-averaged current value when the voltage regulators are turned on, resulting in more stable and balanced current ramping. A predictive multi-phase digital controller may therefore operate according to a target current determined based on a measured or inferred inductor current and an error voltage. Pulse-width, pulse position and pulse frequency (adding or skipping pulses) may be calculated according to the operation of the predictive multi-phase digital controller.

Abstract: A system and method for controlling a converter of a power stage receiving an adapter current for providing current to a load. The converter is operative in a buck mode for charging a battery and in a boost mode for discharging the battery to the load to supplement adapter current. The adapter current is compared with a predetermined level to develop a control signal, and at least one pulse control signal is developed based on the control signal and used to control the modulator. The modulator operates the converter in the buck mode when the adapter current up to the predetermined level, and operates the converter in the boost mode when the adapter current exceeds the predetermined level. The battery current may also be monitored to adjust the control signal to limit battery charge or discharge current in both modes.

Abstract: Methods, devices and systems that perform VC-2 decoding are disclosed. In an embodiment, a VC-2 decoder includes three parallel data paths including top-band, current-band and bottom-band data paths. The top-band data path performs variable length decoding (VLD), inverse-quantization (IQ) and inverse-DC-prediction (IDCP) processing of a top compressed data-band. The current-band data path performs VLD, IQ and IDCP processing of a current compressed data-band. The bottom-band data path performs VLD, IQ and IDCP processing of a bottom compressed data-band. Additionally, the decoder includes a three-level inverse discrete wavelet transform (IDWT) module to perform IDWT processing to synthesize decoded source pixel values in dependence on partially-decompressed top, current and bottom data-bands produced using the three parallel data paths.

Abstract: A DMT system for a half-duplex two-way link carries Internet protocol encoded video stream on a coaxial cable that also carries a baseband rendition of the same video stream. A plurality of downlink symbols modulated on a subband of subcarriers in a downlink signal are decoded. The symbols may carry data encoded on a subband using a constellation of QAM symbols assigned to the subband. Other subbands may be associated with different QAM constellations. Lower-order constellations of QAM symbols may be assigned to subbands that include higher-frequency subcarriers and higher-order constellations of QAM symbols may be assigned to subbands that include lower-frequency subcarriers. A block error correction decoder may be synchronized based on an identification of the first constellation of QAM symbols and information identifying boundaries between the plurality of downlink symbols.