Abstract: A multiple channel programmable gamma correction voltage generator including a resistor ladder, buffers, select logic, and a programmable non-volatile memory device. The memory provides select values indicative of one or more stored gamma correction values. The resistor ladder includes adjustable tap resistors distributed along the resistor ladder. The adjustable tap resistors provide multiple tap voltages distributed according to the gamma correction value. The buffers receive the tap voltages and provide gamma correction voltages. The select logic selects tap points of the adjustable tap resistors to select the tap voltages based on the select values stored in the memory. Additional resistors and switch logic may be included to enable re-positioning of the adjustable tap resistor within the resistor ladder. Latches and address control may be provided on the memory to enable programming and selection of multiple gamma correction values.

Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column.

Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.

Abstract: Conduction loss in the body-diode of a low side MOSFET of a power switching stage of one phase of a coupled-inductor, multi-phase DC-DC converter circuit, associated with current flow in the output inductor of that one phase that is induced by current flow in a mutually coupled output inductor of another phase, during normal switching of that other stage, is effectively prevented by applying auxiliary MOSFET turn-on signals, that coincide with the duration of the induced current, to that low side MOSFET, so that the induced current will flow through the turned-on low side MOSFET itself, thereby by-passing its body-diode.

Abstract: Methods and apparatus of dynamic topology power converters are provided. One method includes monitoring at least one variable of the power converter and based on the at least one monitored variable, using a converter topology selected between at least a full-bridge converter topology and a half-bridge converter topology to achieve an efficient operation at a then current operational load.

Abstract: An integrated circuit is disclosed including a primary input for receiving an input voltage, a battery voltage input for receiving a battery voltage signal and an output for providing an output voltage higher than the battery voltage. First circuitry responsive to the input voltage is provided for turning off the output voltage responsive to an input over voltage condition. Second circuitry responsive to the battery voltage signal is provided for turning off the output voltage responsive to a battery over voltage condition. Third circuitry provides for over current protection.

Abstract: A constant-on-time power-supply controller includes an adder and a control circuit. The adder generates a sum of a sense voltage and a regulated output voltage generated by a filter inductor. The sense voltage is generated by a sense circuit that sources a current to the filter inductor while the inductor is uncoupled from an input voltage, and the sense voltage is related to the current. The control circuit couples the filter inductor to the input voltage for a predetermined time in response to the sum having a predetermined relationship to a reference voltage. Such a power-supply controller may yield a relatively tight regulation of the output voltage even with a power supply having with a low-ESR filter capacitor, and may do so with little or no additional compensation circuitry as compared to prior controllers and with no additional pin on the power-supply-controller chip.

Abstract: A cradle charging system comprises a charging cradle defining a space for a battery of an electronic device. Transformer charging circuitry for charging the battery in the electronic device includes a primary side circuitry for receiving a charging voltage. Secondary side circuitry inductively couples the charging voltage to the battery. The secondary side circuitry provides a controlled output signal based on either constant voltage control or constant current control responsive to a charge level of the battery.

Abstract: A bipolar transient clamp including a RC circuit, a clamping circuit and a breakdown circuit. The RC circuit is configured to control the rate of change of clamp. Moreover, the RC circuit is coupled between a first rail and a second rail. The clamping circuit is configured to pass a current from the first rail to the second rail. In addition, the clamping circuit is coupled to be activated by the RC circuit. The breakdown circuit is coupled between the RC circuit and the clamping circuit. The breakdown circuit is configured to increase the transient trigger voltage of the clamping circuit.

Abstract: A circuit for setting a reference voltage in a floating gate circuit is configured as a precise voltage comparator circuit with a built-in programmable voltage reference. Once the one or more floating gates in the floating gate circuit are set during the a SET operation, the floating gate circuit is configured during a READ mode as a comparator circuit with a built-in voltage reference.

Abstract: A circuit provides multi-module current sharing for circuit modules. The circuit includes an error amplifier having a negative and a positive input and an output. The positive input of the error amplifier is connected to a reference voltage. A buffered differential amplifier has an output connected to the negative input of the error amplifier and a positive and a negative input. A correction current is sourced to the negative input of the buffered differential amplifier. A resistor connected to the negative input of the buffered differential amplifier has a value that controls the amount of current correction applied to the negative input of the buffer differential amplifier by the current correction source.

Abstract: Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three (3) different levels including at least one intermediate level that is coupled to at least one driver. Based on the PWM mode signal, the regulator is switched into a power saving low power operational mode.

Abstract: A system and method is provided for improving the accuracy of the voltage reference output of a floating gate voltage reference circuit by minimizing the temperature coefficient, Tc. The system and method provides a minimized Tc on output reference voltage, for a wide variety of such output voltages. In a dual floating gate voltage reference circuit wherein a voltage reference output (Vref) is generated as a function of the difference in charge of said floating gates, a method includes causing each of the floating gates to change voltage substantially the same amount as a function of temperature such that, during a read mode of the reference circuit, the temperature coefficient, Tc, of the voltage reference output is substantially reduced. The system and method achieves very low Tc over a wide range of reference or comparator voltages using low cost analog test equipment and methods.

Abstract: A method for communicating data over a serial interface between a master device and at least one slave device is disclosed. A master device generates a preamble that is attached to a data block for transmission over the serial interface between a master device and at least one slave device. Upon receipt of the control word at the at least one slave device, the preamble is detected by the slave device. Upon detection of the preamble, the slave device is enabled to respond to information within the control word as appropriate.

Abstract: A drive circuit supplies a drive current to a plurality of light emitting diodes. The drive circuit includes a voltage converter circuit having a particular topology and including at least one inductive element and at least one switching element. The drive circuit senses a current through one of the inductive and switching elements and generates a feedback signal from the sensed current. The feedback signal has a value indicating the drive current being supplied to the light emitting diodes and the drive circuit controls the operation of the voltage converter responsive to the feedback signal.

Abstract: Provided herein are self-calibrating timing circuits and methods for use in a sync separator. A comparator compares a video signal to a video reference voltage to produce a sliced sync signal that has a frequency that is equal to a scan frequency of a horizontal sync embedded in the video signal. A frequency-to-voltage converter converts the sliced sync signal to a voltage control signal having an amplitude that is inversely proportional to the scan period of the horizontal sync embedded the video signal. A voltage-to-timed interval converter that converts the voltage control signal to a timer signal that has timed intervals that are that are inversely proportional to the amplitude of the voltage control signal, and thus proportional to the scan period of the horizontal sync embedded in the video signal.

Abstract: Systems and methods for slow tail compensation are provided. A photodetector signal is pre-amplified to thereby produce an uncompensated photodetector signal that includes a fast component and a slow component. The fast component is removed from the uncompensated photodetector signal to thereby produce a compensating signal that includes the slow component of the uncompensated photodetector signal. The compensating signal is subtracted from the uncompensated photodetector signal to thereby produce a compensated photodetector signal that includes the fast component but not the slow component.

Abstract: A power management IC including a dual purpose pin, a fault detection system, and a fault signature system. The dual purpose pin performs a power management function during normal operation (e.g., a soft start pin coupled to an external capacitor, a set pin coupled to an external resistor, a frequency set pin coupled to a resistor-capacitor combination, etc.). The fault detection system senses any of multiple fault conditions and provides a corresponding fault indicator signal, each indicating a corresponding fault condition. The fault signature system generates a selected fault signature signal on the dual purpose pin, where each fault signature signal has a characteristic indicative of a corresponding fault condition. Thus, an existing pin on the IC is re-used to indicate the fault condition. The fault signature signal may be a unique voltage level, a unique charging rate, a unique frequency signal, or any a combination thereof.

Abstract: A current-limiting switch circuit including a first power semiconductor switch, at least one sense semiconductor switch configured to share a common-gate and a common drain with the first power semiconductor switch, and a second power semiconductor switch serially connected to the first power semiconductor switch and sharing a common node therebetween. The first power semiconductor switch, the first sense semiconductor switch, and the second power semiconductor switch are configured to limit at least a back current.

Abstract: A DC-DC voltage converter is provided that includes a plurality of power channels and a controller. Each power channel is configured to provide a voltage output to an output node of the converter. Each power channel also includes a first sensing circuit configured to provide a primary feedback signal indicative of an output current of the power channel. Each power channel further includes an auxiliary sensing circuit to provided one or more auxiliary feedback signals indicative of an output current of each of the respective other power channels. The controller is configured to control each of the power channels based at least in part on the primary feedback signal and the one or more auxiliary feedback signals.