Patents Assigned to Intersil
  • Publication number: 20040130307
    Abstract: A control circuit for a switch mode DC-DC converter contains an arrangement of monitored LGATE, UGATE and PHASE node condition threshold detectors, outputs of which are processed in accordance with a switching control operator to ensure that each of an upper FET (UFET) and a lower FET (LFET) is completely turned off before the other FET begins conduction, thereby maintaining a dead time that exhibits no shoot-through current and is independent of the type of switching FET.
    Type: Application
    Filed: December 2, 2003
    Publication date: July 8, 2004
    Applicant: Intersil Americas Inc. State of Incorporation: Delaware
    Inventors: Noel Dequina, Donald R. Preslar, Paul K. Sferrazza
  • Patent number: 6759719
    Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: July 6, 2004
    Assignee: Intersil Corporation
    Inventors: Jun Zeng, Gary Mark Dolry, Praveen MurAleedharan
  • Publication number: 20040124818
    Abstract: An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC-DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.
    Type: Application
    Filed: October 14, 2003
    Publication date: July 1, 2004
    Applicants: Intersil Americas Inc.,, State of Corporation : Delaware
    Inventors: Noel B. Dequina, Donald R. Preslar, Paul K. Sferrazza
  • Publication number: 20040125968
    Abstract: A monolithic 1.75 is mounted in a speaker cabinet 1.71 to drive the voice coil 1.74 of the speaker 1.70. The monolithic integrated circuit may be a class D amplifier 1.10, and is at least a half-bridge or full bridge power MOSFET device. Structures and process for forming the mos switching devices 2.20 of the bridge driver circuits are disclosed. Also disclosed is the N+ buried layer 4.14 of the QVDMOS transistors 4.43 of the bridge circuits.
    Type: Application
    Filed: December 15, 2003
    Publication date: July 1, 2004
    Applicant: Intersil Americas Inc.
    Inventors: Lawrence G. Pearce, Donald F. Hemmenway
  • Patent number: 6754195
    Abstract: A wireless communication system configured to communicate using a mixed waveform configuration. The mixed waveform includes a first portion modulated according to a single-carrier scheme with a preamble and header and a second portion modulated according to a multi-carrier scheme. The waveform is specified so that a CIR estimate obtainable from the first portion is reusable for acquisition of the second portion by the receiver. The transmitter may include first and second kernels and a switch, where switch selects the first kernel for the first portion and the second kernel for the second portion to develop a transmit waveform. The receiver may include a single-carrier receiver, a multi-carrier receiver, and a switch that provides a first portion of a signal being received to the single-carrier receiver and a second portion of the signal being received to the multi-carrier receiver.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: June 22, 2004
    Assignee: Intersil Americas Inc.
    Inventors: Mark A. Webster, Michael J. Seals
  • Publication number: 20040108837
    Abstract: A battery charger controller is coupled to DC output terminals of an AC-DC (or DC-DC) adapter containing an AC-DC (or DC-DC) converter. A controlled current flow path between input and output terminals of the battery charger controller circuit is controlled to provide a substantially constant current to charge the battery to a nominal battery voltage. When a constant voltage output of the said adapter transitions to a value that limits available charging current to a value less than programmed constant charging current, current flow drive for the controlled current flow path is increased for a limited time interval. Thereafter, the controlled current flow path gradually reduces charging current as the battery voltage remains at its nominal battery voltage until the charge is complete or otherwise terminated.
    Type: Application
    Filed: December 9, 2002
    Publication date: June 10, 2004
    Applicant: Intersil Americas Inc.
    Inventors: Zheren Lai, Edward Bordeaux, Zen Wu
  • Publication number: 20040108913
    Abstract: A tapped delay line generates a fractional clock pulse signal for controlling a PWM pulse generator, such as used in a DC-DC converter. Operational parameters of the tapped delay are adjusted to maintain a desired fractional precision of the duty-cycle of the PWM clock pulse signal. In a first, phase locked loop (PLL) based embodiment, the tapped delay line-based digital PWM pulse generator includes a compensating phase locked-loop formed around an auxiliary tapped delay line that implements the voltage controlled oscillator of the PLL. In a second embodiment, the PWM pulse generator is configured as an ‘open-loop’ tapped delay line phase detector architecture, which avoids having to correlate parameters of the PLL delay line with those of the PWM delay line.
    Type: Application
    Filed: December 10, 2002
    Publication date: June 10, 2004
    Applicant: Intersil Americas Inc.
    Inventors: Lawrence G. Pearce, William David Bartlett
  • Publication number: 20040095187
    Abstract: A modified Brokaw cell-based circuit produces a current which varies linearly with temperature. The collector-emitter current flow path of a diode-connected transistor is connected in series with the PTAT current produced by a control transistor. The base of the control transistor receives a control voltage whose value defines a limited range of variation of output current with temperature. The output transistor is coupled to an input port of a current mirror, which mirrors the linear collector current from the output transistor. The current through the output transistor is controlled by a composite of a CTAT base-emitter voltage of the diode-connected transistor and a PTAT voltage across a resistor, so that the output transistor produces an output current having a linear temperature coefficient.
    Type: Application
    Filed: November 19, 2002
    Publication date: May 20, 2004
    Applicant: Intersil Americas Inc.
    Inventor: Xuening Li
  • Patent number: 6738273
    Abstract: At least upper order stages of a multi-stage charge pump contain respective drive signal recovery circuits, that enable the charge pump to operate over a larger voltage range and/or be driven by a very small input voltage. The switch control signal recovery circuit has an auxiliary NFET switch whose current flow path is series-coupled with a Schottky diode between the output voltage of the next lower order stage and a PFET switch drive line. The auxiliary switch controllably clamps the PFET switch drive line at a voltage that differs from the output voltage of the next lower order charge pump stage by the voltage drop across the Schottky diode. This effectively guarantees that the level-shifted line of that stage's transient clamp network will be biased to its appropriate operating voltage level, so that the clamp rail of this stage cannot hang up at a voltage level that is well below the output voltage from the next lower order stage.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: May 18, 2004
    Assignee: Intersil Americas Inc.
    Inventor: William Brandes Shearon
  • Publication number: 20040090218
    Abstract: A self-powered overvoltage protection circuit for a regulated DC-DC converter looks for the onset of a very large input voltage prior to regulation. In response to such a voltage during this interval, it turns on a low side electronic power switching device, in accordance with the voltage at one of the phase node and the regulated voltage output terminal from which the protection circuit derives its power. This provides a bypass path for an overvoltage that would otherwise be coupled from the regulated voltage output terminal to one or more load devices.
    Type: Application
    Filed: October 22, 2003
    Publication date: May 13, 2004
    Applicant: Intersil Americas Inc.
    Inventor: Robert Haynes Isham
  • Publication number: 20040090217
    Abstract: A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The reference voltage (VDAC) is boosted by the buffer amplifier 42 to center the droop along the median load. A sensed current signal ICS 22 is proportional to the load current Io 24 and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain Gc. A droop control feedback circuit includes an error amplifier 50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPU max and transformed to the current IDROOP 32 that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output.
    Type: Application
    Filed: September 23, 2003
    Publication date: May 13, 2004
    Applicant: INTERSIL CORPORATION
    Inventors: Volodymyr A. Muratov, Michael Coletta, Wlodzimerz S. Wiktor
  • Patent number: 6734656
    Abstract: A power switching stage architecture for a buck topology-based, DC—DC converter includes an upper power switching N-channel device FET integrated in the same semiconductor circuit chip with the switching driver, while a lower power switching is also an N-channel FET, but is external to the driver chip. Either of the two power switching FETs may be configured to include a pilot FET cell, to facilitate current sensing for the controller.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: May 11, 2004
    Assignee: Intersil Americas Inc.
    Inventors: Greg J. Miller, Michael M. Walters
  • Publication number: 20040085175
    Abstract: An integrated circuit having an inducting device with a symmetric inductor. The inducting device comprises a first and second inductor. The first inductor is formed in a first conductive layer and is approximately symmetric about a plane of symmetry. The second inductor is formed in a second conductive layer that is at a select vertical distance from the first conductive layer. The second inductor is further approximately laterally aligned with the first inductor.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Applicant: INTERSIL AMERICAS INC.
    Inventor: Rex Lowther
  • Patent number: 6731168
    Abstract: A power amplifier linearizer (12) includes an on-chip portion (60) and an external controller (22). The on-chip portion (60) implements two predistortion circuits (86, 88) desirably configured as look-up tables. One predistortion circuit (88) is programmed by the external controller (22) to apply a hotter linearizing translation function (54) and the other predistortion circuit (86) is programmed by the external controller (22) to apply a colder linearizing translation function (56). One or more temperature signals (24, 38) are correlated with the temperatures experienced by a power amplifier (34) and drive a power amplifier thermal modeler (50) implemented in the controller (22). As a result of running the thermal modeler (50), the controller (22) generates an interpolation signal (26) that indicates how far to interpolate between the hotter and colder translation functions (54, 56).
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: May 4, 2004
    Assignee: Intersil Americas, Inc.
    Inventors: David J. Hedberg, James A. Sills, Eric M. Brombaugh
  • Patent number: 6731155
    Abstract: A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS—VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: May 4, 2004
    Assignee: Intersil Americas Inc
    Inventors: J. Mikko Hakkarainen, Kantilal Bacrania, Eric C. Sung, Hsin-Shu Chen, Bang-Sup Song, Mario Sanchez
  • Patent number: 6727745
    Abstract: The integrated circuit includes a power driving device, and a pilot device for sensing current through the power driving device. The pilot device includes a composite pilot having a plurality of series connected transistors and which is at least active while the power driving device is in a linear mode, and a secondary pilot which is active while the power driving device is in a saturation mode. Also, a control circuit activates the secondary pilot.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: April 27, 2004
    Assignee: Intersil Americas Inc.
    Inventors: William Shearon, Salomon Vulih, Donald Preslar
  • Patent number: 6724233
    Abstract: An absolute value circuit includes an operational amplifier, the output of which is coupled to control inputs of complementary polarity transistors having current flow paths therethrough coupled in series with inputs of current mirror amplifier stages. A common node of the current flow paths through the transistors is coupled to an input of the operational amplifier to which a current waveform is applied. The current mirror amplifier stages are configured so as to provide like polarity output currents. The outputs of the current mirror amplifier stages are combined to produce an output current that corresponds to a full wave rectification or absolute value of an input current coupled to the operational amplifier.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: April 20, 2004
    Assignee: Intersil Americas Inc.
    Inventor: Harold Allen Wittlinger
  • Publication number: 20040070382
    Abstract: A multiphase ripple voltage regulator generator employs a hysteretic comparator referenced to upper and lower voltage thresholds. The hysteretic comparator monitors a master ripple voltage waveform developed across a capacitor supplied with a current proportional to the difference between the output voltage and either the input voltage or ground. The output of the hysteretic comparator generates a master clock signal that is sequentially coupled to PWM latches, the states of which define the durations of respective components of the synthesized ripple voltage. A respective PWM latch has a first state initiated by a selected master clock signal and terminated by an associated phase voltage comparator that monitors a respective phase node voltage.
    Type: Application
    Filed: September 29, 2003
    Publication date: April 15, 2004
    Applicant: Intersil Americas Inc.
    Inventors: Michael M. Walters, Xuening Li, Thomas A. Jochum
  • Publication number: 20040070999
    Abstract: At least upper order stages of a multi-stage charge pump contain respective drive signal recovery circuits, that enable the charge pump to operate over a larger voltage range and/or be driven by a very small input voltage. The switch control signal recovery circuit has an auxiliary NFET switch whose current flow path is series-coupled with a Schottky diode between the output voltage of the next lower order stage and a PFET switch drive line. The auxiliary switch controllably clamps the PFET switch drive line at a voltage that differs from the output voltage of the next lower order charge pump stage by the voltage drop across the Schottky diode. This effectively guarantees that the level-shifted line of that stage's transient clamp network will be biased to its appropriate operating voltage level, so that the clamp rail of this stage cannot hang up at a voltage level that is well below the output voltage from the next lower order stage.
    Type: Application
    Filed: October 9, 2002
    Publication date: April 15, 2004
    Applicant: Intersil Americas Inc.
    Inventor: William Brandes Shearon
  • Publication number: 20040066180
    Abstract: A current generator generates a non-linear output current whose temperature coefficient exhibits a prescribed non-linear-to-quasi-linear curvature when a control voltage range is restricted. This particular current characteristic enables a voltage reference employing the current generator for high-order curvature correction to produce an output voltage whose variation is extremely flat over its industry standard operational temperature range.
    Type: Application
    Filed: October 4, 2002
    Publication date: April 8, 2004
    Applicant: Intersil Americas Inc.
    Inventor: William Todd Harrison