Abstract: A battery charger controller is coupled to DC output terminals of an AC-DC (or DC-DC) adapter containing an AC-DC (or DC-DC) converter. A controlled current flow path between input and output terminals of the battery charger controller circuit is controlled to provide a substantially constant current to charge the battery to a nominal battery voltage. When a constant voltage output of the said adapter transitions to a value that limits available charging current to a value less than programmed constant charging current, current flow drive for the controlled current flow path is increased for a limited time interval. Thereafter, the controlled current flow path gradually reduces charging current as the battery voltage remains at its nominal battery voltage until the charge is complete or otherwise terminated.

Abstract: A multiphase synthetic ripple voltage generator for a multiphase DC-DC regulator including a master clock circuit that generates a master clock signal, sequence logic and a ripple regulator for each phase. The DC-DC regulator includes multiple switching circuits, each responsive to a corresponding PWM signal to switch input voltages via a phase node through an output inductor to develop an output voltage. The sequence logic sets each PWM signal in sequential order based on the master clock signal. Each ripple generator includes a transconductance amplifier, a ripple capacitor and a comparator. The transconductance amplifier has an input coupled to a corresponding output inductor and an output coupled to a corresponding ripple capacitor. The comparator has a first input coupled to the ripple capacitor, a second input receiving an error voltage, and an output coupled to the sequence logic for resetting a corresponding PWM signal.

Abstract: A modified Brokaw cell-based circuit produces a current which varies linearly with temperature. The collector-emitter current flow path of a diode-connected transistor is connected in series with the PTAT current produced by a control transistor. The base of the control transistor receives a control voltage whose value defines a limited range of variation of output current with temperature. The output transistor is coupled to an input port of a current mirror, which mirrors the linear collector current from the output transistor. The current through the output transistor is controlled by a composite of a CTAT base-emitter voltage of the diode-connected transistor and a PTAT voltage across a resistor, so that the output transistor produces an output current having a linear temperature coefficient.

Abstract: The present invention relates to an integrated circuit having a MOS capacitor. In one embodiment, a method of forming an integrated circuit comprises forming an oxide layer on a surface of a substrate, the substrate having a plurality of isolation islands. Each isolation island is used in forming a semiconductor device. Patterning the oxide layer to expose predetermined areas of the surface of the substrate. Depositing a nitride layer overlaying the oxide layer and the exposed surface areas of the substrate. Implanting ions through the nitride layer, wherein the nitride layer is an implant screen for the implanted ions. Using the nitride layer as a capacitor dielectric in forming a capacitor. In addition, performing a dry etch to form contact openings that extend through the layer of nitride and through the layer of oxide to access selected device regions formed in the substrate.

Abstract: A DC-to-DC converter includes one or more power switches, a pulse width modulation circuit for generating control pulses for the power switches, and an output inductor connected to the power switches. A thermally compensated current sensor is connected to an intrinsic current sensing element exhibiting a temperature-based parameter non-linearity. The thermally compensated current sensor has a temperature coefficient that substantially matches a temperature coefficient of an intrinsic power converter element used to measure current flow, thus linearizing the current measurement. Also, a current feedback loop circuit cooperates with the pulse width modulation circuit to control the power switches responsive to the thermally compensated current sensor.

Abstract: A system (100) and method (200) for adaptively managing bias of an RF power amplifier (102) is provided. The system (100) incorporates a controller (116) configured to select a radio operating mode. A current-mirror circuit (114) is coupled to the controller (116) and configured to produce a reference current (IRef) as a function of the radio operating mode. A bias regulator (104) is coupled to the controller (116) and the current-mirror circuit (114) and configured to produce a driver-stage bias current (Ib1) and an output-stage bias current (Ib2) for the power amplifier (102) in response to the reference current (IRef). The system (100) also incorporates a DC-to-DC converter (118) coupled to the controller (116) and configured to provide a supply voltage (Vcc) for the power amplifier (102) in response to the radio operating mode. The system (100) also incorporates an envelope detector (120) configured to produce an envelope current (IEnv) in response to an RF input signal (126).

Abstract: A clock signal generator, which requires no clock selection pin includes a multiplexer to which external and internal clocks are applied. The external clock is further coupled directly and via an inverting delay to a logic circuit, the output of which controls a switching device connected across a capacitor. The capacitor is coupled to a current source and to a comparator that is coupled to a reference voltage. The comparator output serves as the select control for the multiplexer. The switching device repeatedly discharges the capacitor in response to the external clock signal, but otherwise allows the capacitor to be charged by the current source. The external clock signal is coupled to the output of the multiplexer, as long as the capacitor is repeatedly discharged by the external clock signal at a frequency sufficient to maintain the voltage across the capacitor less than the reference voltage.

Abstract: A subscriber line interface circuit (SLIC) drive arrangement controllably adjusts DC biasing and overhead voltage characteristics for wireline pair that is optimized for each mode of operation of the SLIC. Respective tip and ring DC drive voltages supplied by tip and ring drive amplifiers are controlled so that the differential DC voltage across the wireline pair has a first constant value during on-hook mode, in which DC loop current may vary between zero and a first DC loop current threshold value associated with a transition from on-hook mode toward off-hook mode. During a transition between on-hook mode and off-hook mode, the tip and ring DC drive voltages are controlled so as to vary the differential DC drive voltage in proportion to monitored DC loop current. During off-hook mode, the differential DC voltage is set at a second fixed value. If an upper DC loop current threshold is reached during off-hook mode, the differential DC voltage is sharply reduced from its second constant value.

Abstract: A circuit arrangement prevents clipping of pulse metering (teletax) signals in a telephone line card channel that results from the differential impedance between a subscriber line interface circuit (SLIC) and the line at the frequency band of teletax signals. The circuit arrangement is configured to sense pulse metering signals through a delay circuit, which is coupled to a reflected signal cancellation circuit. The reflected signal cancellation circuit contains a transconductance amplifier circuit that generates a pair of complementary polarity output currents representative of the sensed teletax signal. One of these output currents is fed back to a programmed impedance element in the transmission channel path of the SLIC so as to effectively cancel the reflected teletax signal.

Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.

Abstract: The present invention relates to inductors with improved inductance and quality factor. In one embodiment, a magnetic thin film inductor is disclosed. In this embodiment, magnetic thin film inductor includes a plurality of elongated conducting regions and magnetic material. The plurality of elongated conducting regions are positioned parallel with each other and at a predetermined spaced distance apart from each other. The magnetic material encases the plurality of conducting regions, wherein when currents are applied to the conductors, current paths in each of the conductors cause the currents to generally flow in the same direction thereby enhancing mutual inductance.

Abstract: A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.

Abstract: An improved base for a NPN bipolar transistor. The base region is formed with Boron and Indium dopants for improved beta early voltage product and reduced base resistance.

Abstract: The present invention relates to inductors with improved inductance and quality factor. In one embodiment, a magnetic thin film inductor is disclosed. In this embodiment, magnetic thin film inductor includes a plurality of elongated conducting regions and magnetic material. The plurality of elongated conducting regions are positioned parallel with each other and at a predetermined spaced distance apart from each other. The magnetic material encases the plurality of conducting regions, wherein when currents are applied to the conductors, current paths in each of the conductors cause the currents to generally flow in the same direction thereby enhancing mutual inductance.

Abstract: Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick material having a predetermined lateral length on the surface of the substrate adjacent the relatively thin dielectric layer. Implanting dopants to form a top gate using a first edge of the first region as a mask to define a first edge of the top gate. Implanting dopants to form a drain contact using a second edge of the first region as a mask to define a first edge of the drain contact, wherein the distance between the top gate and drain contact is defined by the lateral length of the first region.

Abstract: A soft start circuit for a DC-DC converter has an input reference voltage coupled to an error amplifier and to a soft start capacitor. A feedback resistor is coupled between an output node and the error amplifier, whose output is coupled to a pulse width modulator (PWM). The PWM output is coupled through an inductor to the output node, to which an output capacitor referenced to ground is coupled. Means is provided to charge up the soft start capacitor to the output voltage while the converter is disabled. As a result, when enabled, the converter will not discharge the output capacitor, but will ramp the output voltage to the voltage Vref without excessive currents.

Abstract: A high bandwidth, feed-forward oscillator generates a ramp or sawtooth voltage for controlling the operation of a pulse width modulator-based, switched DC power supply circuit. The oscillator is operative to effectively immediately adjust the slope of each rising and falling portion of the ramp/sawtooth signal, as necessary, in proportion to the magnitude of the input voltage, while maintaining the frequency of the ramp waveform effectively constant. A comparator network establishes a difference between peak and valley portions of the sawtooth in accordance with input voltage. In response to a change in input voltage a control circuit modifies the value of the difference between the peak and valley portions to define a new set of respective peak and valley portions VpeakNEW and VvalleyNEW, and immediately causes the sawtooth waveform to transition to the new set of respective peak and valley portions VpeakNEW and VvalleyNEW at said prescribed frequency.

Abstract: A tapped delay line generates a fractional clock pulse signal for controlling a PWM pulse generator, such as used in a DC-DC converter. Operational parameters of the tapped delay are adjusted to maintain a desired fractional precision of the duty-cycle of the PWM clock pulse signal. In a first, phase locked loop (PLL) based embodiment, the tapped delay line-based digital PWM pulse generator includes a compensating phase locked-loop formed around an auxiliary tapped delay line that implements the voltage controlled oscillator of the PLL. In a second embodiment, the PWM pulse generator is configured as an ‘open-loop’ tapped delay line phase detector architecture, which avoids having to correlate parameters of the PLL delay line with those of the PWM delay line.

Abstract: A feed forward pulse width modulator compares a ramp signal with a control voltage to control respective states of a pulse width modulation signal. A respective cycle of the ramp signal is generated by charging a capacitor with a charging current that is proportional to input voltage until the voltage across the capacitor reaches a peak threshold that is also proportional to the input voltage. The capacitor is thereupon discharged with a discharging current proportional to the input voltage until the voltage across the capacitor reaches a (non-zero) valley threshold.

Abstract: A method of determining electrical parameters of inductive elements includes a novel technique of inverting an impedance matrix representative of said inductive circuit element. The method reduces model simulation time by a factor of 3000. In one embodiment, simulation time of a device model was reduced from 1 hour to less than 3 seconds. The method is suitable for use with circuit element modeling tools, circuit simulation environments, and antenna modeling systems. The method may be applied to inductors, transformers, antennas, etc.