Abstract: The present invention relates to the field of electrically erasable and programmable nonvolatile semiconductor memories (EEPROM) and, in particular, to contactless array configurations that are used for the practical and efficient implementation of a particular type of memory transistor. Such a memory transistor allows fast 5V-only programming by the use of an enhanced source-side injection mechanism. This concept requires a program gate in the field oxide region which serves to capacitively couple a high voltage to the floating gates. Thus, a very high injection current is established during programming. This additional program gate, however, increases the cell area considerably. The present disclosure shows a contactless 5V-only Flash EEPROM array configuration that relies on shared program lines in order to minimize the area overhead that is caused by this program gate. Furthermore, a memory array with shared wordlines is presented which further enhances the density achievable.

Abstract: The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes.

Abstract: The present invention relates to processes for fabrictation of Vertical MISFET devices or a stack of several Vertical MISFET devices having high fabrication yield.

Abstract: A hardware and software co-design environment and design methodology based on a data-model that allows one to specify, simulate, and synthesize heterogeneous hardware and software architectures from a heterogeneous specification. The environment and methodology of the invention allow for the interactive synthesis of hardware and software interfaces. The environment defines primitive objects to represent a specification of an essentially digital system. The primitive objects are defined by describing the specification of the system in one or more processes, each process representing a functional aspect of the system. Further, each of the processes have ports which are connected to ports of other processes with a channel. The ports structure communication between the processes.

Abstract: The present invention concerns a method of generating code for a programmable processor and comprises several steps. The first step is representing the processor as a directed bipartite graph with first and second sets of vertices and with edges, the graph comprising essentially all information about an instruction set and hardware of the processor, the first set of vertices representing storage elements in the processor, and the second set of vertices representing operations in the processor. The second step includes linking the graph to tools and libraries required for generating code for the processor. The last step is executing the required code generation phases, whereby the required information about the processor is extracted from the graph. The present invention also concerns the application of this method.

Abstract: The present invention relates to the field of electrically erasable and programmable nonvolatile semiconductor memories (EEPROM) and, in particular, to contactless array configurations that are used for the practical and efficient implementation of a particular type of memory transistor. Such a memory transistor allows fast 5 V-only programming by the use of an enhanced source-side injection mechanism. This concept requires a program gate in the field oxide region which serves to capacitively couple a high voltage to the floating gates. Thus, a very high injection current is established during programming. This additional program gate, however, increases the cell area considerably. The present disclosure shows a contactless 5 V-only Flash EEPROM array configuration that relies on shared program lines in order to minimize the area overhead that is caused by this program gate. Furthermore, a memory array with shared wordlines is presented which further enhances the density achievable.

Abstract: A system for evaluating the thermal impedance of packaged semiconductor chips. The measuring apparatus includes a thermostatic bath filled with a dielectric liquid and a temperature sensor for measuring the temperature of the bath. The semiconductor chip is subjected to a calibration step followed by a thermal response measurement step. Increasing the power pulse length allows measurement of the steady-state junction-to-case thermal resistance. The measuring apparatus and method is further used for tracing in-situ degradation of packaged semiconductor chips due to power cycling.

Abstract: A differential pair of optoelectronic pnpn devices provided with probing impedances allows such pair to operate as an optical to optical, optical to electrical and electrical to optical transceiver. This basic transceiver is useful in situations where information transport is needed between two or more locations, e.g., optical interconnects in electronic computing systems. The transceiver can be repeated in arrays in connection with Si-VLSI circuitry for high bandwidth optical interconnect applications.

Abstract: In an optical projection system for use in projection printing of masks to wafers, comprising an illumination system including a light source and a mask positioned in the optical path of the illumination system, an optical phase structure is positioned in the optical path between the light source and the mask. The phase structure comprises a pattern of distributed transparent features having at least one refractive index, the transparent features of said phase structure being related in position and orientation to the opaque features of the mask.

Abstract: A device for detecting infrared radiation which comprises a sensitive arm which, over at least a portion of its length, consists of bimetal. One end of said arm is joined to a membrane.

Abstract: An integrated tunable optical filter comprising a substrate made of a semiconducting material. The substrate includes first and second sections. The first section forms a tunable transmission filter, based on a codirectional coupler having a low selectivity. The second section forms a reflection filter with a reflection spectrum containing a number of peaks. A first injector, designed for current injection into said first section, is provided. Thus, the filter response of the first section is shifted in wavelength over a large wavelength range. There is also a second injector, designed for current injection into the second section. As a result, the reflective spectrum of the second section is slightly shifted in wavelength, in such a way that one reflection peak of the reflection spectrum corresponds to the coupling wavelength of the first section. Consequently, the total filter response has a very narrow bandwidth and wide tunability.

Abstract: A method for measuring the resistance or conductivity between two or more conductors which are placed against a semiconductor element, the conductors are placed either in contact with the top surface or one conductor is placed in contact with the top surface and the other conductor is in the form of a large ohmic contact applied to the bottom surface of the semiconductor element. In order to bring the contact resistance between the top conductor(s) and the element to, and hold it at, a predetermined value during measuring, the conductor(s) are held at a constant distance and/or under constant pressure relative to the semiconductor element by use of a scanning proximity microscope. The top conductor may have a boron implanted diamond tip. The carrier profile of the semiconductor element is determined from previously derived calibration curves.

Abstract: A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.

Abstract: A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.

Abstract: The system comprises a latent image detection device comprising an alignment device which uses non-actinic radiation (10) and which is intended for aligning the mask pattern with respect to the substrate (3) and is designed for detecting the measure of coincidence of a mask alignment feature and a substrate alignment feature (8). The alignment device is provided with a radiation-sensitive detection system (6) which is connected to an electronic signal circuit in which the amplitude of the radiation incident on the detection system is determined, which originates from a latent image, formed in the photosensitive layer, of a mask feature, in which a spatial frequency occurs which is approximately equal to the useful resolving power of the projection lens system and considerably greater than the resolving power of the alignment device.

Abstract: A method of fabricating a plurality of optoelectronic components on a semiconductor substrate, each optoelectronic component comprising several layers grown in a reactor. Every layer is being grown under a predetermined individual pressure. The active layers of all the components are lying substantially at the same height. Control of the pressure in the reactor during growth allows the thickness of the layer grown to be constant or to vary over the substrate area.

Abstract: A method for measuring the resistance or conductivity between two or more conductors which are placed against a semiconductor element, wherein in order to bring the contact resistance between the conductors and the element to, to hold it at,a predetermined value during measuring, the conductors are held at a constant distance and/or under constant pressure relative to the semiconductor element.

Abstract: A circuit element which includes a source region of a first conductance type provided with a source terminal, an intermediate region of the first conductance type separated from the source region by a first volume, a first channel region portion of a second conductance type provided with a first gate terminal and occupying the first volume, a drain region of the first conductance type provided with a drain terminal and separated from the intermediate region by a second volume, a second channel region portion of the second conductance type provided with a second gate terminal conductively connected to the first gate terminal and occupying said second volume, and an oxide layer. The first channel region portion, the intermediate region, and the second channel region portion are deposited on one face of the oxide layer. The design of the circuit element reduces adverse consequences of the so-called Kink effect, to which other circuit elements have been subject.

Abstract: Method and apparatus for measuring the radiation originating from one side of a wafer of semiconductor material using a pyrometer, wherein non-blackbody compensation radiation is projected onto that side to compensate for the reflectivity of the wafer of material and wherein the intensity of the non-blackbody compensation radiation is controlled subject to the amount of radiation measured by the pyrometer.

Abstract: A process of developing a photoresist by contacting the photoresist with a developer is improved by subjecting the photoresist to heat prior to completion of the development process.