Abstract: A method of efficiently simulating logic designs comprising signals that are capable of having more than two unique decimal values and one or more unique drive states, such as designs based upon the new N-nary logic design style, is disclosed. The present invention includes a signal model that models N-nary signal value, drive strength, and signal definition information in a specific format that supports the ability of the simulator to simulate the operation of the N-nary logic gates such as adders, buffers, and multiplexers by arithmetically and logically manipulating the unique decimal values of the N-nary signals. The simulator comprises an input logic signal model reader, an arithmetic/logical operator, an output logic signal model generator, and an output message generator that generates one or more output- or input-signal-specific output messages that pack relevant simulation data into a format optimized to the architecture of the simulation host.

Abstract: The present invention is a grid that is a monitor that detects a cross product of design verification events and reports a single status event to a database. One embodiment of the present invention comprises axes declarations, logic expressions, and a grid declaration. An axes declaration produces a cross product of verification events. A logic expressions evaluates whether a specific verification event has occurred. A grid declaration returns the status event. The present invention further comprises a grid where the cross-product of verification events comprises a fully or a sparsely populated cross-product of verification events. Additionally, the present invention further comprises a grid that uses N-Nary signals. And, the present invention comprises a parser to translate the monitor source file code into a standard computer language code.

Abstract: A logic device with improved capacitance isolation and a design methodology that reduces parasitic capacitance is disclosed. The logic device includes a virtual ground node, a plurality of input signals that may be individual wires of one or more N-NARY signals, and two or more discharge paths. Each discharge path includes an evaluate node, one or more transistors gated by the input signals, and one or more intermediate nodes, one of which is coupled to the virtual ground node. In one embodiment, the discharge paths are perfectly isolated from each other for every combination of inputs. In another embodiment, intermediate nodes on discharge paths maybe electrically coupled to the evaluation path only at the intermediate node coupled to the virtual ground node.

Abstract: The present invention is a 5:2 carry-save-adder (CSA) that receives the five input signals I0, I1, I2, I3 and I4 and computes the two output signals SUM and CARRY. The 5:2 CSA comprises a first level of logic circuitry and a second level of logic circuitry. The first level of logic circuitry comprises a plurality of adders and receives the input signals and generates three intermediate terms T0, T1, and T2. The second level of logic circuitry comprises a carry logic circuit and a sum adder, and uses the intermediate terms to compute the two output signals SUM and CARRY. The 5:2 CSA of the present invention operates using either binary signals or N-NARY signals.

Abstract: A method and apparatus that performs anticipatory rounding of intermediate results in a floating point arithmetic system while the intermediate results are being normalized is disclosed. One embodiment of the present invention includes four logic levels, implemented in N-NARY logic. In the first three logic levels, propagation information is gathered for preselected bit groups from the coarse and medium shift output of the normalizer as those results become available. In the fourth level, an incremented, normalized intermediate single-precision or double-precision mantissa result is produced by combining fine shift output bit values with propagation information for the appropriate top bit group, middle bit group, and bottom bit group. The appropriate bit groups are determined by examining the value of the fine shift select signal.

Abstract: The present invention comprises a method and apparatus for a pipeline of functional units with a late pipe functional unit that executes instructions without stalling until the result is available. The present invention comprises one or more earlier functional units coupled to a late pipe functional unit. The late pipe functional unit does not begin executing instructions until all of the input operands are or will be available for execution so that the late pipe functional unit will execute instructions without stalling until the result will be available in a fixed number of cycles. The present invention further comprises a late pipe functional unit that may comprise a floating point unit, a graphics unit, or an enhanced floating point unit. And finally, the late pipe functional unit is non-stalling and or is non-cancelable.

Abstract: The present invention is a method and apparatus for building a software system in a networked software development environment, utilizing existing software version control and build tools such as RCS and MAKE. Source and object files are loaded into network caches shared by multiple users at local workstations. At individual workstations, a cache link structure generated from a user-created build list is provided to the software building program, which then builds the desired software system using links to cached files. The present invention thus minimizes the amount of computing resources required to build software programs by eliminating the need to store multiple local copies of building block software files, and to rebuild object files that may be unchanged from prior builds. A method for maintaining and updating network caches to maximize the efficiency of cache link creation is also disclosed.

Abstract: The present invention is a dynamic logic propagation delay targeting tool that includes a gate target delay initializer 90, a levelizer 82, a backward logic scanner 94, a forward logic scanner 96, a gate target delay incrementor 97, and a gate target delay comparator 97 that together calculates the propagation delay of a signal in a specified block of dynamic logic.

Abstract: The present invention is a method and apparatus for building a software system in a networked software development environment, utilizing existing software version control and build tools such as RCS and MAKE. Source and object files are loaded into network caches shared by multiple users at local workstations. At individual workstations, a cache link structure generated from a user-created build list is provided to the software building program, which then builds the desired software system using links to cached files. The present invention thus minimizes the amount of computing resources required to build software programs by eliminating the need to store multiple local copies of building block software files, and to rebuild object files that may be unchanged from prior builds. A method for maintaining and updating network caches to maximize the efficiency of cache link creation is also disclosed.

Abstract: The present invention comprises a number transformer that includes an encoder that converts binary numbers to N-NARY numbers. Within an N-NARY number, exactly one of the bits has a value of one and all of the remaining bits have a value of zero. According to some aspects, several N-NARY numbers are generated in response to a binary number. A set of encoding instance selectors defines a partitioning of the bits of the binary number and a range of bits within each partition. The encoder then converts each subset of bits of the binary number to a corresponding N-NARY number, such that exactly one of the bits of each N-NARY number has a value of one and all of the remaining bits of the N-NARY number have a value of zero, and such that the one of the bits of each N-NARY number having a value of one is within the range of bits defined by the corresponding encoding instance selector. The set of encoding instance selectors may define a test point within a circuit under test, and may be produced by an on-chip ROM.

Abstract: A method and apparatus for random-access scan of a network of dynamic logic or N-nary logic, wherein the network includes sequentially clocked precharge logic gates and one or more scan gates is disclosed. Each clocked precharge logic gate and each scan gate further comprise a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers. Each scan gate further comprises a scan circuit that accepts scan control signals and couples to one or more scan registers in a RAM-like architecture. A scan control circuit generates scan control signals and scan timing signals which operate to capture the state of the output buffers of the scan gate and provide that state to one or more scan registers.

Abstract: The present invention is a method and apparatus that initializes N-NARY logic and dynamic logic to a special stress mode. The present invention has a logic circuit that includes a shared logic tree with one or more evaluate nodes, one or more precharge devices, and an evaluate device. Coupled to the evaluate nodes is a state generation control circuit that generates a state signal. A state generation circuit receives the state signal from the state generation control circuit and initializes the evaluate nodes to a functionally illegal state that initializes the logic circuit to the special stress mode. One embodiment of the present invention initializes the evaluate nodes to a low state. When the first logic circuit in a series of logic circuits is initialized to the functionally illegal state, the present invention will initialize the succeeding logic circuits in the series as each phase in the different clock domains evaluate, which initializes the succeeding logic circuits to the special stress mode.

Abstract: The present invention discloses an apparatus and method for determining the speed of a logic circuit relative to the clock. The preferred embodiment utilizes dynamic logic to deliver a critical signal to a transition detection circuit, which performs the OR/NOR function on the signals. In one embodiment the transition detection circuit comprises static logic. In another embodiment, the transition detection circuit comprises an N-NARY gate that performs the OR/NOR function.

Abstract: The present invention is a dynamic logic propagation delay targeting tool that includes a gate target delay initializer 90, a levelizer 82, a backward logic scanner 94, a forward logic scanner 96, a gate target delay incrementor 97, and a gate target delay comparator 97 that together calculates the propagation delay of a signal in a specified block of dynamic logic.

Abstract: The present invention discloses a method and apparatus that uses extensions to the TLB entry to dynamically identify pages of memory that can be weakly ordered or must be strongly ordered and enforces the appropriate memory model on those pages of memory. Such identification and memory model enforcement allows for more efficient execution of memory instructions in a hierarchical memory design in cases where memory instructions can be executed out of order. From the page table, the memory manager constructs TLB entries that associate page frame numbers of memory operands with page-granular client usage data and a memory order tag. The memory order tag identifies the memory model that is currently being enforced for the associated page of memory. The memory manager updates the memory order tag of the TLB entry in accordance with changes in the client usage information. In the preferred embodiment, the TLB structure is a global TLB shared by all processors.

Abstract: A design tool to support design of a N-NARY logic circuit is described. The designer develops a syntax statement that comprises encoded information according to a defined syntax governing signal naming, logical function, and circuit performance. The encoded syntax statement describes the desired logical function of the N-NARY logic circuit and the specific configuration of transistors required to build the N-NARY logic circuit. The syntax statement is provided to a compiler that processes and decodes the syntax statement, and generates from the syntax statement a behavioral model of the N-NARY circuit and a physical circuit description of the N-NARY circuit.

Abstract: The present invention is an apparatus that supports multiple assignment code, comprising a register that may be assigned multiple values, instructions that receive a value and dispatch a result, a first queue that stores the results of an instruction during a pipeline stall, and a second queue that stores the state of the register when an interrupt is taken. The value assigned to a register may be available for processing only after a latency period has passed. The value received by an instruction from a register is the most recent value assigned to the register for which the latency period has passed. The first queue eliminates the need for global stalls in the context of various pipeline implementations. The second queue allows for interruptibility. The present invention further comprises a mode where the software identifies that it does not intend to exploit multiple assignment code.

Abstract: The present invention discloses an apparatus and method for determining the speed of a logic circuit relative to the clock. The preferred embodiment utilizes dynamic logic to deliver a critical signal to a transition detection circuit, which performs the OR/NOR function on the signals. In one embodiment the transition detection circuit comprises static logic. In another embodiment, the transition detection circuit comprises an N-NARY gate that performs the OR/NOR function. The output of the transition detection circuit is fed into a series of delayed flip-flop latches, which determine when the critical signal transitioned from the pre-charge state relative to the clock.

Abstract: The present invention is an incrementor that receives as inputs a 32-dit 1-of-4 operand and a 1-of-2 increment control signal. For each dit of the operand, the present invention determines whether the increment control signal, which is treated as a carry into the least significant dit, propagates into said dit. If so, the value of the dit is incremented. Otherwise, the dit value is output without modification. The present invention also generates a carry out signal if the increment control signal has propagated across all dits.

Abstract: A design tool to support design of logic circuits is described. The designer develops a syntax statement that comprises encoded information to a defined syntax governing signal naming, logical function, and circuit performance. The encoded syntax statement describes the desired logical function of the logic circuit and the specific configuration of transistors required to build the logic circuit. The syntax statement is provided to a compiler that processes and decodes the syntax statement, and generates from the syntax statement a behavioral model of the logic circuit and a physical circuit description of the logic circuit.