Abstract: The present invention comprises a method and apparatus that selectably performs either addition or subtraction on two N-nary operands to generate an intermediate, then final, N-nary final result. If the intermediate result of the operation contains less bits than a full register, the intermediate result is “merged” with the second operand in that unaltered bits from the second operand are bypassed to the final result. Accordingly, the final result and the second operand have an equal number of bits.

Abstract: The present invention includes a partial register write handler. The write handler receives either two or three operands. An execution unit operates on portions of two operands, rather than on full operands. The result of the execution unit has fewer bits than an “additional” operand, which may be any of the two or three operands received by the write handler. An output multiplexer receives all of the bits of an execution unit result and selected bits of the additional operand, and produces an output that has as many bits as the additional operand. If the output of the multiplexer is a string of bits, the string of bits contains the execution unit result as a substring of bits. The remaining bits of the output of the multiplexer are selected from the additional operand.

Abstract: The present invention comprises a multi-function shifter that uses N-nary logic and includes an operation selection and various 1-of-N multiplexers to support a variety of shift modes. The shift modes include rotates, logical shifts in which 0 is shifted into any vacated bit positions, and arithmetic shifts in which the value of the original most significant bit is shifted into any vacated bit positions. The present invention includes a general 32-bit shifter that can shift an arbitrary number of places in a single cycle, using any of the modes described above.

Abstract: An apparatus that performs arithmetic logic and carry-lookahead logic in parallel on two N-nary operands, including saturating or unsaturating, signed or unsigned, addition or subtraction. The operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. For multiple partitions, carry propagation is interrupted on partition boundaries. Each selectable feature may be implemented singly, or in combination with other selectable features.

Abstract: An apparatus and method for performing saturating addition or subtraction on two signed or unsigned operands using N-NARY logic. The two operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. For multiple partitions, carry propagation is interrupted on partition boundaries so that partitions may be saturated independently.

Abstract: The present invention comprises a number transformer that includes at least one updatable parameter, for example a ring counter, that produces an N-nary number. The N-nary number has several bits, exactly one of which has a value of one and the remaining of which have a value of zero. The number transformer also includes a masker, configured to perform a bitwise boolean AND upon the first updatable parameter and a binary number. The binary number is obtained from a linear finite state machine operating as a pseudorandom pattern generator. When several ring counters are included, multiplexers are added to select one of the ring counters. The multiplexers are controlled by a ROM, that iterates through the various test points in a circuit under test.

Abstract: A syntax statement describing an N-NARY or a CMOS logic circuit having one, and only one, possible configuration of transistors is disclosed. The syntax statement comprises a signal naming convention and one or more gate instantiations using a gate instantiation syntax that includes one or more gate output signal variables described using the signal naming convention, one or more gate operators, and one or more gate expressions using a gate expression syntax that is interpreted to describe the specific transistor configuration of the logic circuit. The signal naming convention includes one or more of the following fields: optional bit and descriptor, signal degree, evaluation, and clock phase. The gate expression syntax further comprises one or more of the following syntaxes: mux select, arithmetic, logical, multiple output, capacitance isolation, or shared node.

Abstract: The present invention comprises a master global clock distributed in a low-skew manner over a relevant clock domain area coupled with a plurality of locally generated clocks in said clock domain area. The plurality of locally generated clocks are tuned to allow for skew and jitter tolerance. The present invention further comprises embodiments with 3, 4, 5, and 6 locally generated clocks.

Abstract: The described multiplier provides the signed or unsigned product of a multiplicand and multiplier represented in preferably 1-of-4 N-NARY signals by performing a preferably radix-four Booth recoding of the multiplier, producing partial products using a plurality of Booth multiplexers, summing the partial productsto produce two intermediate partial products using a six-level Wallace tree, and summing the two intermediate partial products using a carry lookahead adder. The Booth encoding is performed at the dit level using encoding circuitry implemented in N-NARY logic.

Abstract: An enhanced floating point unit that supports floating point, integer, and graphics operations by combining the units into a single functional unit is disclosed. The enhanced floating point unit comprises a register file coupled to a plurality of bypass multiplexers. Coupled to the bypass multiplexers are an aligner and a multiplier. And, coupled to the multiplier is an adder that further couples to a normalizer/rounder unit. The normalizer/rounder unit may comprise a normalizer and a rounder coupled in series and or a parallel normalizer/rounder. The enhanced floating point unit supports both integer operations and graphics operations with one functional unit.

Abstract: An apparatus and method that perform partitionable carry-lookahead logic on two N-nary operands. The operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. The present invention performs carry-lookahead logic to calculate a block carry-lookahead indicator for a grouping, or block, of bits. The present invention forces the block indicator to a “Halt” value if the block comprises the most significant block within a partition, thus interrupting the carry propagation chain on partition boundaries. The present invention supports interruption of the carry propagation chain for both addition and subtraction.

Abstract: A method and apparatus for random-access scan of a network of dynamic logic or N-nary logic, wherein the network includes sequentially clocked precharge logic gates and one or more scan gates is disclosed. Each clocked precharge logic gate and each scan gate further comprise a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers. Each scan gate further comprises a scan circuit that accepts scan control signals and couples to one or more scan registers in a RAM-like architecture. A scan control circuit generates scan control signals and scan timing signals which operate to capture the state of the output buffers of the scan gate and provide that state to one or more scan registers.

Abstract: The present invention comprises a method and apparatus for built-in self-test of logic circuitry for logic under test. The logic under test comprises a plurality of test points, each test point having a plurality of nodes. The test circuitry comprises a linear finite state machine. The linear finite state machine generates subsequent states that are non-sequential, pseudorandom binary numbers stochastically determined by a characteristic polynomial of the linear finite state machine. Moreover, the contents of the linear finite state machine are readable or writable via scan. The preferred implementation also comprises a test data bus coupled between the logic under test and the linear finite state machine. The test data bus is configured to convey data in parallel fashion between the linear finite state machine and the selected test point of the plurality of test points.

Abstract: An apparatus that takes two N-nary operands and selectably performs either addition or subtraction on them to produce an arithmetic result and a carry indicator. Carry-lookahead logic is utilized to create HPG signals for each N-nary dit of the intermediate sum of the two operands and also to create “block” HPG indicators for blocks of dits. In the preferred 1-of-4 embodiment, subtraction may be implemented as four's complement addition. The value of each dit of the intermediate sum is incremented by one before final output if a carry has propagated into the dit.

Abstract: The present invention is a method and apparatus that synchronizes logic in an integrated circuit (IC). The present invention discloses a global clock signal with a global phase and an approximately 50% duty cycle. Additionally, the present invention discloses a first local clock signal with a first phase and an approximately 50% duty cycle that couples to a first dynamic logic gate where the first local clock signal is generated from the global clock signal. One or more intermediate local clock signals with one or more intermediate phases are generated from the global clock signal where each intermediate local clock signal has an approximately 50% duty cycle that couples to one or more intermediate dynamic logic gates. An end local clock signal with an end phase and an approximately 50% dutycycle that is also generated from the global clock signal and that couples to an end dynamic logic gate.

Abstract: The present invention discloses a method and apparatus that uses extensions to the TLB entry to dynamically identify pages of memory that can be weakly ordered or must be strongly ordered and enforces the appropriate memory model on those pages of memory. Such identification and memory model enforcement allows for more efficient execution of memory instructions in a hierarchical memory design in cases where memory instructions can be executed out of order. From the page table, the memory manager constructs TLB entries that associate page frame numbers of memory operands with page-granular client usage data and a memory order tag. The memory order tag identifies the memory model that is currently being enforced for the associated page of memory. The memory manager updates the memory order tag of the TLB entry in accordance with changes in the client usage information. In the preferred embodiment, the TLB structure is a global TLB shared by all processors.

Abstract: The present invention is a method and apparatus for an N-NARY logic circuit that uses N-NARY signals. The present invention includes a shared logic tree circuit that evaluates one or more N-NARY input signals and produces an N-NARY output signal. The present invention additionally includes a first N-NARY input signal coupled to the shared logic tree circuit and a second N-NARY input signal coupled to the shared logic tree circuit. The shared logic circuit evaluates the first second and second N-NARY input signal and produces an N-NARY output signal coupled, which additionally couples to the shared logic tree circuit. The present invention uses signals that include 1 of 2 N-NARY signals, 1 of 3 N-NARY signals, 1 of 4 N-NARY signals, 1 of 8 N-NARY signals, and the general 1 of N N-NARY signals. The present invention evaluates any given function that includes the AND/NAND, OR/NOR, or XOR/Equivalence functions.

Abstract: The present invention allows the logic state of a clocked precharge (CP) logic gate to be tested when stopping or starting the logic gate's clock and comprises a plurality of clock signals with overlapping phases and a plurality of CP logic gates coupled in series. Each CP logic gate of the plurality of CP logic gates is coupled to an individual clock signal. The present invention further comprises one or more signal keeper devices coupled to certain individual CP logic gates in the critical path of the logic state. The signal keeper device allows the state of the plurality of CP logic gates to be tested when stopping or starting the individual clock signal of an individual logic gate of said plurality of logic gates. The present invention is suitable for a variety of testing techniques that includes IDDQ, scan testing, and hardware emulation testing.

Abstract: The present invention discloses an apparatus and method for performing carry propagate logic on two 1-of-4 two-bit addends to produce a 1-of-3 carry propagate indicator. The preferred embodiment of the present invention will set an H indicator for a given dit n if the sum of An and Bn is less than or equal to two, will set a P indicator if the sum is three, and will set a G indicator if the sum is greater than three.

Abstract: The present invention uses N-nary logic to perform addition or subtraction, along with carry propagate logic, within one gate. The gate produces as outputs a 1-of-4 result value and a 1-of-3 HPG indicator. The preferred embodiment of the present invention implements subtraction using three's complement addition. In an alternative embodiment, four's complement addition is implemented to achieve the subtract function and the HPG indicator is a 1-of-2 signal that combines the H(alt) and P(rop) indications.