Abstract: The present invention utilizes N-nary logic to implement an add function and a carry-lookahead function within the same gate, producing an N-nary sum and an N-nary HPG indicator.

Abstract: The present invention is a magnitude comparator that receives as inputs two 32-bit 1-of-4 operands. The magnitude comparator generates a carry indicator if the value of the first operand is less than or equal to the value of the second operand. The magnitude comparator generates a no carry indicator if the value of the first operand is greater than the value of the second operand.

Abstract: The present invention discloses a method and apparatus for adding two 1-of-N addends to produce a 1-of-N sum. In the preferred embodiment, the addends and sum comprise 1-of-4 logic signals.

Abstract: The present invention is a method and apparatus of routing a 1 of 4 signal to reduce the effective signal coupling between the signal wires. The present invention is a wire pack with a first, second, third, and fourth wire for routing a 1 of 4 signal in a semiconductor device. While routing the wires of the wire pack, the present invention rotates the route of each individual wire to reduce the signal coupling between the wires. Additionally, an isolation barrier borders the outside of the wire pack to further reduce the signal coupling. The rotation of the wires allow each individual wire to be adjacent to each other wire for ½ of the wire's route.

Abstract: The present invention is an apparatus and method for two-stage address generation that uses pipelining to avoid one level of latency in certain address-generation situations. The first level of the present invention contains redundant three-lever hardware that performs pre-add logic on 32-bit or 16-bit operands. The pre-add logic circuit for 32-bit operands comprises three carry-save adders. For 16-bit operands, the pre-add logic circuit comprises a four-port three-level 16-bit adder. The second stage comprises a three-logic level adder that adds two operands. The method of the present invention avoids one level of latency for simple address generation, although both stages are always utilized. For complex address generation, both latency cycles are required. Regarding dependent generation, the present invention provides a single-cycle latency bypass datapath that also avoids one level of latency.

Abstract: The present invention is a method and apparatus of routing a 1 of N signal to reduce the effective signal coupling between the signal wires. The present invention is a wire pack with a plurality of wires for routing a 1 of N signal in a semiconductor device. While routing the wires of the wire pack, the present invention rotates the route of each individual wire to reduce the signal coupling between the wires. Additionally, an isolation barrier borders the outside of the wire pack to further reduce the signal coupling. The rotation of the wires allow each individual wire be adjacent to each other wire for part of the wire's route. Other embodiments of the present invention include routing 1 of 3 signals and 1 of 4 signals.

Abstract: The present invention describes a method and apparatus that performs parallel normalization and rounding on an ANSI/IEEE 754-1985 floating point intermediate result that dispenses with the need for shifting of the intermediate result prior to normalization or rounding. The exponent is pre-incremented prior to normalization. During normalization, the most significant bit of the intermediate fraction is shifted into the carry bit and the exponent is decremented accordingly. Selection logic then selects one of six possible formatting procedures to generate a mathematically correct output fraction in proper ANSI/IEEE 754-1985 floating point format, and formatting logic generates the output fraction according to the selected formatting procedure.

Abstract: A memory device having a sense trigger coupled to receive an address when available, and to assert a sense trigger signal to the sense trigger when the sense trigger receives the address. The memory device also has an N-NARY, or 1-of-N, input logic gate that provides additional assurance that no more than one word line is asserted when an address is decoded. The memory device also has an N-NARY, or 1-of-N, output driver logic gate that provides an output signal directly useful for providing to another (N-NARY) 1-of-N logic gate.

Abstract: The present invention describes an apparatus and method that normalizes an ANSI/IEEE 754-1985 floating point arithmetic intermediate result having a fraction and exponent. The exponent is pre-incremented by one prior to normalization. During normalizaion, the most significant binary “1” of the fraction is shifted left until it resides in the carry bit. For each left shift performed, the incremented exponent is decremented once.

Abstract: The present invention describes an apparatus and method to select the format of the output fraction result of an ANSI/IEEE 754-1985 floating point arithmetic operation where parallel normalization and rounding of the intermediate fraction result has occurred. The C bit and the L bit and the most significant bit of the intermediate fraction are examined, along with the Gin bit, Rin bit, and round control bit. Based on these inputs, the output fraction is formatted by performing zero or more manipulations of either the output of the rounder circuit or the output from the normalizer circuit.

Abstract: The present invention describes an apparatus and method that formats the output fraction result of an ANSI/IEEE 754-1985 floating point arithmetic operation where parallel normalization and rounding of the intermediate fraction result has occurred. The output fraction is formatted using all or some of the bits from the output of either the rounder circuit or the normalizer circuit.

Abstract: The present invention comprises a logic device with improved capacitance isolation and a design methodology for reducing unwanted parasitic capacitance in logic circuits. The logic device further comprises an output signal having a first internal evaluate node and a second evaluate node. Additionally, the logic device comprises a first input signal that has a first input wire and a second input wire where the first input wire corresponds to a first possible value of the first input signal and the second input wire corresponds to a second possible value of the first input signal. The logic device further comprises a first plurality of intermediate nodes that includes a first intermediate node. Additionally, the logic device includes a first plurality of transistors that further includes a first transistor coupling the first internal evaluate node to the first intermediate node and being gated by the first wire of the first input signal.

Abstract: The present invention comprises a plurality of clock signals with an approximately 50% duty cycle and overlapping phases. The phases of the plurality of clocks are such that the phase of an individual clock signal overlaps the phase of an earlier clock signal by an amount equal to the overlap of the phase of the next clock signal. The present invention further comprises a plurality of clocked precharge (CP) logic gates coupled in series. An individual CP logic gate couples to an individual clock signal though the CP logic gate's evaluate device. For the data flow through the individual CP logic gate, the logic gate receives its data input from an earlier CP logic gate in the series and passes to the next CP logic gate in the series. The earlier CP logic gate couples to an earlier phase clock signal, and the next CP logic gate couples to the next phase clock signal.

Abstract: The present invention comprises a method and apparatus for a logic circuit with constant power consumption. The logic circuit comprises a 1 of P first input signal that further comprises a plurality of wires wherein each wire of said plurality of wires has equal capacitive loading. The logic circuit additionally comprises a 1 of Q second input signal that comprises a plurality of wires wherein each wire of said plurality of wires has equal capacitive loading. A logic tree circuit couples to the first input signal and the second input signal. The logic tree circuit generates a result for a 1 of R output signal, which couples to the logic tree circuit. The 1 of R output signal comprises a plurality of wires wherein each wire of said plurality of wires has equal capacitive loading. The power consumption of the logic circuit is independent of the value of the first signal or the second signal, which results in the logic circuit having constant power consumption.

Abstract: The present invention is a method and apparatus for a register cell that is configured to store information. The cell includes a multiplexer that is configurable to select various inputs when the multiplexer is in various states. The multiplexer is configurable to select a first input when the multiplexer is in a first state, and to select a second input when the multiplexer is in a second state. The multiplexer is further configured to provide storage data, the first input being configured to receive data from outside the cell. An output element, such as a second multiplexer, is configured to receive a word enable. The output of the first multiplexer is delayed in a delay element, and is provided as one of the inputs to the first multiplexer.