Abstract: A data access method for serial bus is provided. During a write/read cycle, the write/read cycle is divided into a plurality of transmitting intervals and a plurality of suspending intervals. In each of the transmitting intervals, a clock signals is transmitted on a clock pin and a data signals is transmitted on a data pin. In each of the suspending intervals, the clock signals stop being transmitted on the clock pin. In other words, the present invention uses an interrupted clock signal, such that an embedded controller can directly write a received data in a flash memory or directly output the data read from the flash memory, so as to avoid using any register. Therefore, the present invention can decrease the cost of the embedded controller and reduce the area of integrated circuit.

Abstract: An embedded controller includes a keyboard interface, a keyboard signal conversion unit, a flash memory control unit, and a selection unit. When the selection unit couples the flash memory control unit to the keyboard interface according to an indication signal, a remote controller is coupled to the keyboard interface so as to input an input signal to the embedded controller through the keyboard interface. And the flash memory control unit decodes the input signal and writes it into a flash memory to change a data stored in the flash memory.

Abstract: An LED driver and a display device using the same are disclosed. The LED driver is adapted for driving a first set of LEDs and a second set of LEDs. The LED driver includes an inductor, a main switch, a first switch, a second switch, and a controller. The inductor has a first terminal receiving an input voltage. The main switch is coupled between a second terminal of the inductor and a common level for adjusting a current flowing therethrough. The first switch is coupled between the first set of LEDs and the second terminal of the inductor. The second switch is coupled between the second LEDs and the second terminal of the inductor. The controller is coupled to controlling terminals of the main switch, the first switch, and the second switch respectively for controlling conducting statuses of the main switch, the first switch, and the second switch respectively.

Abstract: A data processing apparatus for loop structure is provided. The apparatus includes a fast memory device and a loop detector. The loop detector is coupled to a processor to detect whether the processor performs a loop structure or not. When the processor performs the loop structure, the loop detector outputs a control signal. According to the control signal, the apparatus stores a loop structure data corresponding to the loop structure in the fast memory device for the processor to perform the loop structure.

Abstract: A data processing apparatus for loop structure is provided. The apparatus includes a fast memory device and a loop detector. The loop detector is coupled to a processor to detect whether the processor performs a loop structure or not. When the processor performs the loop structure, the loop detector outputs a control signal. According to the control signal, the apparatus stores a loop structure data corresponding to the loop structure in the fast memory device for the processor to perform the loop structure.

Abstract: A multiple output stage converter (MOSC) and an operating method thereof are provided. The MOSC includes a first transistor, a second transistor, a third transistor, and a logic control module. A terminal of the first transistor, a terminal of the second transistor, and a terminal of the third transistor are coupled to a power source via an inductor. Another terminal of the first transistor is coupled to a first output terminal. Another terminal of the second transistor is coupled to a second output terminal. Another terminal of the third transistor is coupled to a ground voltage. The logic control module is used to control the on/off state of the second transistor. The well of the second transistor is floating when the first transistor or the third transistor is on. The well of the second transistor is floated or coupled to the second output terminal when the second transistor is on.

Abstract: A bandgap reference circuit, taking two or more power supplies as the input power supply for outputting a reference voltage, includes a first reference circuit, a second reference circuit, a power selection circuit and a switch circuit. The first and second reference circuits receive two respective power supplies for producing first and second voltages, respectively. As the power selection circuit takes the first power voltage level as the input voltage, the power selection circuit outputs a first control signal; while the power selection circuit takes the second power voltage level as the input voltage, the power selection circuit outputs a second control signal. The switch circuit is coupled to the power selection circuit, the first reference circuit and the second reference circuit. As the switch circuit receives the first control signal, it outputs the first voltage; while the switch circuit receives the second control signal, it outputs the second voltage.

Abstract: The present invention provides a control device of the memory, which accelerates the memory to execute iterant commands. This control device includes a micro-controller unit, a controller, a block information table and a state machine. Among them, the micro-controller unit is used to issue a command to operate the memory, which contains several blocks. The controller is coupled between the memory and the micro-controller unit. When it determines the command needs not be executed repeatedly, the micro-controller unit would issue the command through the control device. When the command is determined necessary for repetitive execution, the state machine would repeatedly carry out this command. The state machine performs an analysis based on the state of every block in the block information table and executes repetitively the command accordingly. It also updates the state information on the blocks in the table accordingly.

Abstract: A multiple output stage converter (MOSC) and an operating method thereof are provided. The MOSC includes a first transistor, a second transistor, a third transistor, and a logic control module. A terminal of the first transistor, a terminal of the second transistor, and a terminal of the third transistor are coupled to a power source via an inductor. Another terminal of the first transistor is coupled to a first output terminal. Another terminal of the second transistor is coupled to a second output terminal. Another terminal of the third transistor is coupled to a ground voltage. The logic control module is used to control the on/off state of the second transistor. The well of the second transistor is floating when the first transistor or the third transistor is on. The well of the second transistor is floated or coupled to the second output terminal when the second transistor is on.

Abstract: A Delta-Sigma analog-to-digital converter and a method thereof are provided. According to a non-overlapping clock signal, the Delta-Sigma analog-to-digital converter performs an integration process on the difference between a plurality of input signals and the corresponding feedback signals to generate an integrated signal. Then, according to a selecting signal, the integrated signal is selectively output. Afterward, according to a latch signal, the selectively output integrated signal is quantized and latched by only one quantizer, thereby generating a digital output signal correspondingly. Accordingly, by using only one quantizer, the present invention can have the same function as the prior art which uses a plurality of quantizers, thereby decreasing the occupied chip area.

Abstract: A control circuit for a power converter and the power converter using the control circuit are provided. The power converter includes an energy-storing inductor. The control circuit includes a first switch component and a duty cycle control circuit. The first switch component is coupled to the energy-storing inductor to control the energy-storing inductor to store energy. The duty cycle control circuit receives a digital value and a clock signal to count enable times of the clock signal. When the enable times of the clock signal reach the digital value, the duty cycle control circuit controls the first switch component to suspend the energy-storing inductor from storing energy.

Abstract: A control device for a memory is provided. The control device includes a micro-control unit (MCU), a command queue, a command sequencer, and a table. The control device is coupled to the memory and is used for controlling the memory to execute an operation. In which, the MCU outputs a control signal according to the operation. The command sequencer sequentially stores command sets required by the execution of the operation according to the control signal, and each command set includes plural commands. The command queue sequentially stores command set contents according to the order of the corresponding command sets. The table stores a target address of the memory required by the execution of the operation.

Abstract: An audio encoder includes a time-frequency mapping block, a psychoacoustic model block, a middle/side (M/S) encoding block, a parameter calculation block, a bit allocation and quantization block and a bitstream formatting block. The encoder is forced to operate in M/S mode for reducing the calculation time of the parameter used for bit allocation, quantization and encoding. In addition, the calculation of the parameter only needs to consider the middle and side channels but not the left and right channels, thus the complexity of the psychoacoustic model for analyzing the input audio signal can be reduced.

Abstract: A multi-processor system comprises a clock generator, a clock controller, a main processor, a plurality of co-processors and an interrupt control interface. Because the main processor and the co-processors need not work together to deliver the processing result, the multi-processor system may be designed that each processor in the multi-processor system is independently switched to operate at lower clock or power down completely according to the feedback of the hardware performance detection for each processor when the whole system is in active usage. This means on-demand power saving for the multi-processor system, so as to save power greatly.

Abstract: A signal converting apparatus for integrating an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) and an integration unit thereof are provided. The present invention integrates ADC and DAC, that do not operate simultaneously, into a signal converting apparatus (SCA), wherein a control signal decides whether an analog-to-digital mode or a digital-to-analog mode is selected. By sharing the operational amplifiers and other components in the SCA, the chip area and the cost are significantly reduced. In addition, in the integration unit, by switching a plurality of capacitor sets with various capacitances, the capacitance coefficients required for switching ADC and DAC are obtained.