Abstract: An audio amplifier including a differential mode integrator, a first comparator, a second comparator, a logic circuit and a driving unit is provided. The differential mode integrator receives a differential input signal and a differential output signal and outputs a differential mode intermediate signal. The first comparator has a positive input terminal receiving a first terminal signal of the differential mode intermediate signal, a negative input terminal receiving a ramp signal, and generates a first signal. The second comparator has a positive input terminal receiving a ramp signal, a negative input terminal receiving a second terminal signal of the differential mode intermediate signal, and generates a second signal. The logic circuit performs a logic operation on the first and second signals to generate a third signal and a fourth signal. The driving unit generates a differential output signal to drive a load according to the third and fourth signals.

Abstract: A multimedia playing method is provided. First, N audio files selected by a user are received, wherein N>0. Then, the memory space required for playing each of the N audio files for a predetermined time is respectively detected. Next, whether total memory space required by the N audio files is not smaller than a predetermined value is determined. If the total memory space required by the N audio files is not smaller than the predetermined value, the predetermined time is reduced and the step of respectively detecting the memory space required for playing each of the N audio files for the predetermined time is executed again. If the total memory space required by the N audio files is smaller than the predetermined value, an initial part of each of the N audio files to be played for the predetermined time is stored into the memory.

Abstract: A data access method for serial bus is provided. During a write/read cycle, the write/read cycle is divided into a plurality of transmitting intervals and a plurality of suspending intervals. In each of the transmitting intervals, a clock signal is transmitted on a clock pin and a data signal is transmitted on a data pin. In each of the suspending intervals, the clock signal stop being transmitted on the clock pin. In other words, the present invention uses an interrupted clock signal, such that an embedded controller can directly write a received data in a flash memory or directly output the data read from the flash memory, so as to avoid using a plurality of registers. Therefore, the present invention can decrease the cost of the embedded controller and reduce the area of the integrated circuit.

Abstract: An efficient system and method for adaptive tile depth filter (ATDF) is disclosed. The key concept of this system and method is to consider more occlusion conditions in order to achieve a better performance of filter before the conventional Z test process in three dimensional graphics pipeline. Two occlusion criteria, Zmax and Zmin (depth range in a tile), are introduced first for occlusion and non-occlusion fragments in a tile. The points between Zmax and Zmin are in uncertain fragment which may need to go through the later Z test. Moreover, a new technique, coverage mask, can further filter the points in the uncertain fragment to a final uncertain fragment and non-occlusion fragment. Besides, the coverage mask can be used to efficiently decide which tile needs the further sub-tile depth filter.

Abstract: A class-D amplifier and a method of generating a multi-level output signal thereof are provided. The class-D amplifier includes a controlling logic circuit and an output module. The controlling logic circuit analyzes the amplitude of an input signal to generate a voltage modifying signal. A power supply provides a voltage according to the voltage modifying signal. The controlling logic circuit generates controlling signals according to the input signal. The output module generates an output signal to drive a load according to the voltage and the controlling signals. In other words, the resolution of the amplitude of the output signal is increased by modifying the voltage, and a signal to noise ratio is then increased.

Abstract: A temperature measuring method and a temperature measuring apparatus using the same are provided. In the method, four different currents are provided to a temperature measuring device respectively so as to obtain four different voltages at two ends of the temperature measuring apparatus correspondingly. A ratio of two of the four different currents is equal to a ratio of the other two currents. Next, two voltage variation values are obtained according to mentioned four different voltages. One of the voltage variation values is converted to a first digital temperature code representing a first temperature, and the other voltage variation value is converted to a second digital temperature code representing a second temperature. Then, a real temperature code representing a real temperature is obtained according to the first digital temperature code and the second digital temperature code.

Abstract: A current detection apparatus including a current detection circuit, a voltage regulation power supply circuit, and a package carrier is disclosed. The current detection circuit has a reference terminal and a detection terminal. The voltage regulation power supply circuit is used to generate an output voltage and includes a current transmission terminal for transmitting a current. The package carrier is used to carry the current detection circuit, the voltage regulation power supply circuit, a reference pad, and a current transmission pad. The package carrier includes at least one common voltage lead. The current transmission pad is coupled to the reference pad through at least one bonding wire such that an equivalent resistance is formed on the coupling path between the current transmission pad and the reference pad.

Abstract: A light-emitting device driving circuit and a method thereof are provided. A terminal of a light-emitting device is coupled to a supply voltage and a cathode of a diode via an inductor, and the other terminal is coupled to an anode of the diode. The light-emitting device driving circuit includes a switch, a current-sensing circuit, and a switch control circuit. The current-sensing circuit is coupled to the anode of the diode via the switch to determine whether or not to generate a turning-off control signal according to a conducting-current value of the switch. The switch control circuit controls an on/off state of the switch, and turns off the switch according to the turning-off control signal. Besides, the switch control circuit compares the conducting-current value with a reference-current value to generate a comparing result to dynamically adjust a time length of turning off the switch accordingly.

Abstract: An integrated storage device and a control method thereof are provided. The integrated storage device includes an interface controller, a microcontroller, a plurality of non-volatile storage devices, and a channel link controller. The interface controller retrieves a master control signal and a slave control signal sent by a motherboard. The microcontroller generates a selecting signal. The non-volatile storage devices have at least two storage types. The non-volatile storage devices are divided into a first group of storage device and a second group of storage device according to the selecting signal. The channel link controller respectively controls the first group of storage device and the second group of storage device according to the master control signal and the slave control signal. Thereby, the accessing efficiency of the integrated storage device is increased.

Abstract: An auto-addressing method for a series circuit and an auto-detecting method for detecting the number of circuits connected in series are disclosed. The series circuit includes a number of same integrated circuits connected in series. The auto-detecting method is based on the auto-addressing method. In the auto-addressing method, the integrated circuits are enabled to transmit an initial address command sequentially. Each integrated circuit is provided with corresponding address information upon receiving the initial address command.

Abstract: A digital image converting apparatus with auto-correcting phase and a method thereof are provided. The digital image converting apparatus includes a phase controller, a delay locked loop (DLL), an analog-to-digital converter (ADC) and a position adjuster. The phase controller selects one of preset phases for outputting and continuously changes the output preset phase for controlling a clock signal produced by the delay locked loop. The ADC converts an analog display frame according to the adjusted clock signal. After all the preset phases are output in sequence, the phase controller can obtain an optimal phase for converting the display frame according to the smallest front porch of horizontal scan line and the smallest back porch of horizontal scan line of a digital display frame produced by the position adjuster.

Abstract: A class-D amplifier and a method of generating a multi-level output signal thereof are provided. The class-D amplifier includes a controlling logic circuit and an output module. The controlling logic circuit analyzes the amplitude of an input signal to generate a voltage modifying signal. A power supply provides a voltage according to the voltage modifying signal. The controlling logic circuit generates controlling signals according to the input signal. The output module generates an output signal to drive a load according to the voltage and the controlling signals. In other words, the resolution of the amplitude of the output signal is increased by modifying the voltage, and a signal to noise ratio is then increased.

Abstract: A data preserving method and a data accessing method for a non-volatile memory are provided. In the data preserving method, a data is checked according to an error correcting code (ECC) to obtain an error bit number of the data. When the error bit number is greater than a threshold, the data is moved from a first memory unit to a second memory unit and is corrected according to the ECC. Thereby, the data stability of the non-volatile memory is improved.

Abstract: An LED driver and a display device using the same are disclosed. The LED driver is adapted for driving a first set of LEDs and a second set of LEDs. The LED driver includes an inductor, a main switch, a first switch, a second switch, and a controller. The inductor has a first terminal receiving an input voltage. The main switch is coupled between a second terminal of the inductor and a common level for adjusting a current flowing therethrough. The first switch is coupled between the first set of LEDs and the second terminal of the inductor. The second switch is coupled between the second LEDs and the second terminal of the inductor. The controller is coupled to controlling terminals of the main switch, the first switch, and the second switch respectively for controlling conducting statuses of the main switch, the first switch, and the second switch respectively.

Abstract: A control device for a memory is provided. The control device includes a micro-control unit (MCU), a command queue, a command sequencer, and a table. The control device is coupled to the memory and is used for controlling the memory to execute an operation. In which, the MCU outputs a control signal according to the operation. The command sequencer sequentially stores command sets required by the execution of the operation according to the control signal, and each command set includes plural commands. The command queue sequentially stores command set contents according to the order of the corresponding command sets. The table stores a target address of the memory required by the execution of the operation.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: A boost/buck and DC/DC power converter with a charging function, a method thereof and a system incorporating the same are disclosed. The system uses an external power supply or a rechargeable battery as the power thereof. The power converter regulates the external power supply for producing the output voltage. An inductor-based booster/bucker further boosts or bucks the produced output voltage and the boosted or bucked output voltage charges the rechargeable battery.

Abstract: An electro-static discharge protection circuit including a first-LDNMOS transistor, a second-LDNMOS transistor, a first-resistor, and a gate-driven resistance is provided. The drain of the first-LDNMOS transistor is served as an electro-static input end, the P-body and source of the first-LDNMOS transistor are connected to each other. A coupling-voltage signal determines whether the first-LDNMOS transistor is turned on or not. The drain, P-body, and gate of the second-LDNMOS transistor are respectively connected to the drain of the first-LDNMOS transistor, the source of the first-LDNMOS transistor, and a common-ground potential. The first-resistor is connected between the source of the first-LDNMOS transistor and the common-ground potential.

Abstract: A constant-current driving circuit includes a first current source, a reference voltage generating circuit and an output signal generating circuit. A terminal of the first current source is coupled to a terminal of a first LED string, wherein the terminal of the first current source has a first voltage. The reference voltage generating circuit is used for generating a reference voltage and comparing the first voltage with a first predetermined voltage to generate a first comparing signal to thereby adjust the reference voltage. The output signal generating circuit is used for outputting an output signal to another terminal of the first LED string and receiving the input signal, wherein the output signal generating circuit decides whether or not to output the input signal serving as the output signal according to the comparison result of the reference voltage with the second voltage.

Abstract: A Delta-Sigma analog-to-digital converter and a method thereof are provided. According to a non-overlapping clock signal, the Delta-Sigma analog-to-digital converter performs an integration process on the difference between a plurality of input signals and the corresponding feedback signals to generate an integrated signal. Then, according to a selecting signal, the integrated signal is selectively output. Afterward, according to a latch signal, the selectively output integrated signal is quantized and latched by only one quantizer, thereby generating a digital output signal correspondingly. Accordingly, by using only one quantizer, the present invention can have the same function as the prior art which uses a plurality of quantizers, thereby decreasing the occupied chip area.