Abstract: An electronic device includes a first machine assembly, a second machine assembly, a first sensor, a second sensor, and a control circuit. The second machine assembly is pivoted to the first machine assembly. The first sensor is located on the first machine assembly and configured to generate first sensing data when the electronic device is in a non-normal working state. The second sensor is located on the second machine assembly and configured to generate second sensing data when the electronic device is in the non-normal working state. The control circuit is coupled to the first sensor and the second sensor and configured to perform a first default operation according to the first sensing data and the second sensing data.

Abstract: An apparatus for waking up a computer system is disclosed. The apparatus is electrically coupled to a south bridge, or a Platform Controller Hub (PCH), having a first USB host interface.

Abstract: A key module and a signal generating method of the key module are provided. The key module is suitable for an electronic device, the electronic device has a processing system, and the key module includes a detecting module and a controller. The detecting module includes a main electrode conductor and an assisting electrode conductor, where the assisting electrode conductor is disposed around the main electrode conductor. The controller is coupled to the main electrode conductor and the assisting electrode conductor. When the controller determines that a touch is detected by the main electrode conductor, but not detected by the assisting electrode conductor, the controller transmits a key signal to the processing system.

Abstract: A solution is provided to flexibly choose a combination of flash memory devices to reduce the overall cost of the flash memory devices or increase the overall utilization of the flash memory devices, while satisfying the capacity requirements for the flash memory devices in a system design, wherein a decoding unit is used for determining which flash memory devices will be accessed and re-mapping incoming serial addressing bits, for accessing one flash memory device, into an outgoing serial addressing bits for accessing another flash memory device.

Abstract: A data-processing module can handle a predetermined command transmitted by a corresponding main controller through a command serial signal or a clock signal. When the predetermined command represents “command-latching”, the data-processing module controls a command register to store the data transmitted by a section of the command serial signal temporarily stored in an FIFO buffering circuit for latching command. When the predetermined command represents “data-latching”, the data-processing module controls a command register to store the data transmitted by the section of the command serial signal temporarily stored in the FIFO buffering circuit for latching data. In this way, the data-processing module can control the command register to latch command or the data register to latch data without a redundant pin for receiving latching signals transmitted by the main controller, reducing the cost of the data-processing module.

Abstract: A load driving apparatus is disclosed. The load driving apparatus includes a driving signal generator and a controller. The driving signal generator is used for providing a driving signal to a load. The controller is used for generating and providing a control signal to the driving signal generator. The driving signal generator generates N integer signals and M fractional signals in a driving period to form the driving signal according to the control signal. N and M are positive integers, and an amplitude of the integer signals is greater than an amplitude of each of the fractional signals.

Abstract: The invention provides a communication method, which is applicable for a detection system, and a control end apparatus as well as a detection apparatus using the same method. According to one aspect of the invention, the invention proposes a communication method, which is applicable for communications between a detection system and a control end apparatus, and includes following procedures: the detection system transmitting a first digital television signal to a control end apparatus, and the first digital television signal include one or more video signals; and the control end apparatus transmits a second digital television signal to the detection system, where the second digital television signal includes one or more control commands.

Abstract: A flash memory storage system includes a flash memory, a host and a controller is provided. The controller couples to the host and the flash memory, and restricts the host to access the flash memory according to a state of the host. When the host is in a booting state or in a resetting state, the controller allows the host to access the flash memory. After the host completes a booting process or a resetting process, the controller restricts the host to access the flash memory so as to protect a data stored by the flash memory. Besides, a data protection method for which applied to the above-mentioned storage system is also provided in the present invention.

Abstract: A position apparatus of a touch device and a position method thereof are provided, wherein the touch device includes a plurality of scan lines. In the position method, a plurality of capacitances in the scan lines are sensed. Next, a plurality of capacitances respectively sensed in an ith scan line of the scan lines and a subset of the scan lines neighboring with the ith scan line are selected. When the capacitance sensed in the ith scan line is larger than each of the capacitances sensed in the subset of the scan lines, the capacitance sensed in the ith scan line is determined as a peak capacitance. Finally, a touch position is calculated according to the peak capacitance and the capacitances sensed in the subset of the scan lines.

Abstract: A bridge system includes a request device, connected to a first bus; a target device, connected to a second bus; and a bridge, communicated with the first bus and the second bus, and the bridge has a buffer, wherein when the request device asks the bridge for reading data of a target address from the target device, a transaction is started, and the bridge asks the target device to transfer data of the target address and following addresses, and then the target device retrieves and transfers the data of the target address and following addresses to the bridge, that is stored in the buffer and then transferred to the request device in turn, and wherein as amount of transferred data to the request device reaches a threshold, the bridge continuously asks data of a following address of the target device before the transaction is finished.

Abstract: A method for transmitting extra information in digital TV broadcast contents, comprising: retrieving video contents from an electronic apparatus; acquiring the extra information of the electronic apparatus; encoding the video contents into encoded video contents; encoding the extra information into a graphic subtitle or a text subtitle; providing a service information/program specific information table; multiplexing the encoded video and audio contents, the graphic subtitle or the text subtitle, and the service information/program specific information table to generate a transport stream; and transmitting the transport stream.

Abstract: A touch panel is disclosed. The touch panel mentioned above includes at least a touching detection column and a touching detection module. The detection column includes N first touching detection units, N is a positive integer. Each of the first touching detection units transfers a first capacitance varying value according to an area cover by a touching point. The touching detection module operates a differential operating on the first capacitance varying values from two of the first touching detection units which is disposed adjoining in sequential for obtaining a capacitance varying order distribution. The touching detection module obtains a number of at least one first touching point and coordinates thereof by calculating the capacitance varying order distribution.

Abstract: The primary object of the present invention is to provide a data accessing method for a multi level cell type non-volatile memory, including a plurality of storage cells, each storage cell has 0th˜Mth bits, each Kth bit of the storage cells respectively form a Kth order bit page, wherein 0?K?M, the data accessing method comprising: mapping a logical page onto a plurality of physical pages when a computer system is going to access the multi-level cell type non-volatile memory; taking a plurality of temporary data storage blocks of the multi-level cell type non-volatile memory For data accessing by the computer system based on the multi-level cell type non-volatile memory; and providing a page jumper to only select the Kth order bit page of physical pages to store in one temporary data storage block.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.

Abstract: A digital wireless transmitter is disclosed. The digital wireless transmitter includes an interface, used to receive an audio signal and/or a video signal, the digital wireless transmitter is pluggable into an electronic device via the interface; a digital modulator, coupled to the interface, the digital modulator is used to modulate the audio signal and/or the video signal into a digital television signal; and a RF front end circuit, coupled to the digital modulator, the RF front end circuit is used to transform the digital television signal to a RF signal on a predetermined band.

Abstract: A capacitance interface circuit is provided. An external inductive capacitor is divided into a variable portion and an invariable portion. The capacitance of an internal adjustable capacitor is designed to be equal or close to the fixed capacitance of the external inductive capacitor. The internal adjustable capacitor is used for storing charges having a polarity opposite to that of the invariable portion of the external inductive capacitor in order to neutralize the effect of the invariable portion of the external inductive capacitor. Thus, a charge converter composed of a fully-differential amplifier and feedback capacitors needs only work on the variable portion of the external inductive capacitor, and accordingly the accuracy in subsequent data processing is increased.

Abstract: A channel estimation apparatus and a method for the same are provided. The channel estimation apparatus includes a preamble buffer unit, a gain adjusting unit, a demodulation unit, and an estimation unit. The preamble buffer unit receives and temporarily stores a plurality of symbols in preamble signal. The symbols correspond to a plurality of gain control values. The gain adjusting unit adjusts the symbols to a plurality of gain normalized symbols according to the gain control values. The demodulation unit receives the gain normalized symbols and demodulates the same to obtain a frequency domain demodulation signal. The estimation unit receives the frequency domain demodulation signal and performs a channel estimation about the frequency domain demodulation signal and a frequency domain reference value of a standard preamble signal, so as to obtain a channel frequency response.

Abstract: A digital image converting apparatus with auto-correcting phase and a method thereof are provided. The digital image converting apparatus includes a phase controller, a delay locked loop (DLL), an analog-to-digital converter (ADC) and a position adjuster. The phase controller selects one of preset phases for outputting and continuously changes the output preset phase for controlling a clock signal produced by the delay locked loop. The ADC converts an analog display frame according to the adjusted clock signal. After all the preset phases are output in sequence, the phase controller can obtain an optimal phase for converting the display frame according to the smallest front porch of horizontal scan line and the smallest back porch of horizontal scan line of a digital display frame produced by the position adjuster.