Abstract: A semiconductor diode array monolithically integrated onto a power MOS transistor or power IGBT for temperature sensing. With the application of a positive bias and a constant current, the diode array provides a voltage that varies linearly as a function of temperature for the power transistor. The diode array is constructed in such a manner so as to prevent latch-up (i.e. where a parasitic silicon controlled rectifier is turned on, locking the power transistor in an on condition) and voltage breakdown (i.e. where the diode malfunctions from excessive voltage). The diode array includes at least three diodes that are either in parallel or are in series. The two types of diode array can be used in either a high-side driver circuit or a low-side driver circuit.

Abstract: A method and apparatus for providing a substantially constant current from a voltage source. The apparatus includes a depletion mode transistor connected to a parallel network of resistors. At least one of the resistors is provided with a series fusible link so as to enable removal of one or more of the resistors from the network and adjust the output of the current limiter to a desired value.

Abstract: A simplified process of making an insulated gate transistor entails forming the active regions in a single diffusion step. The method includes the steps of implanting and diffusing impurities of a first conductivity type (p for n-channel devices), implanting and diffusing a heavy dose of impurities of the same conductivity type (p+ for n-channel devices), and implanting and diffusing impurities of the other conductivity type (n+ for n-channel devices), wherein the three types of impurities are diffused at the same time in the same step. In a preferred embodiment of an n-channel process, the p-type dopant is boron and the n-type is arsenic.

Abstract: A technique for providing dual direction current sensing with a single current mirror configured to provide the same current ratio in both directions for at least one predetermined temperature. The invention contemplates any of a number of techniques for providing relatively increased diode conduction in the mirror in order to provide the same current ratio as when channel conduction is the sole mechanism. These include increasing the doping of the cell body, increasing the diode area per cell relative to the amount of MOS channel area, providing extra diode cells in the mirror, or locating the current mirror in the hottest part of the chip where diode conduction is greatest.

Abstract: An hermetic package for power semiconductor devices is disclosed. The package includes a generally rectangular cavity with leads extending through the walls thereof. The bottom of the cavity is defined by a base which includes a pair of mounting tabs protruding from opposite corners thereof. The mounting tabs are configured to allow the packages to be nested together. A cover attached to the walls provides a hermetically sealed package.

Abstract: A technique for sensing the temperature of power MOS devices contemplates a main transistor and monolithically formed sense transistor. A resistor, which may integrated into the device or may be off chip, is connected between the respective source nodes of the main transistor and the sense transistor (as in a normal current mirror). However, the respective gate nodes of the main transistor and the sense transistor are not directly connected to each other (in contrast to the normal current mirror configuration where the respective gate nodes of the main transistor and the sense transistor are directly connected). Rather, the sense transistor gate node is coupled to the output terminal of an operational amplifier. The amplifier, has a first input terminal coupled to a reference voltage and a second, complementary, input terminal coupled to the sense transistor source node.

Abstract: A semiconductor diode monolithically integrated onto a power MOS transistor or power IGBT for temperature sensing. With the application of a positive bias and a constant current, the diode provides a voltage that varies linearly as a function of temperature for the power transistor. The diode is constructed in such a manner so as to prevent latch-up (i.e. where a parasite silicon controlled rectifiers is turned on, locking the power transistor in an on condition) and voltage breakdown (i.e. where the diode malfunctions from excessive voltage).

Abstract: In a DMOS power device, a current sensing apparatus comprises bonding pads arranged in specific locations with at least one current sense pad having active cells thereon and a source pad which is separated from the current sense pad. The configuration of cells provides that sources are tied together by a metal layer, which, due to its specific resistance, forms a resistance path between the source pad and the current sense pad or more specifically between the points of contact of a Kelvin lead of the source pad and the current sense pad. The invention has the advantages that substantially the entire chip area is utilized for conduction of power currents and that internal components form a resistive path for current to voltage conversion.

Abstract: A method and apparatus for annealing devices having radiation induced damage is disclosed. A device is exposed to electron irradiation to induce damage to the active area. The device is then annealed with a rapid thermal anneal at a low temperature. The rapid thermal anneal may, optionally, be followed by a conventional oven or furnace anneal at a temperature of about 300.degree. to 450.degree. C. The method produces devices having improved and well controlled characteristics such as short circuit operating area, power dissipated during switching, and on-state voltage drop.

Abstract: An hermetic package for power semiconductor devices is disclosed. The package includes a generally rectangular cavity with leads extending through the walls thereof. The bottom of the cavity is defined by a base which includes a pair of mounting tabs protruding from opposite corners thereof. The mounting tabs are configured to allow the packages to be nested together. A cover attached to the walls provides a hermetically sealed package.

Abstract: One or more probe cells are use to sense voltage and current accurately and without affecting performance of the switching device (T.sub.1) or the load. In addition, power, resistance, and temperature can be determined from the voltage and current. Voltage sensing is accomplished by placing a large value resistor (R.sub.3) (much greater than the on-resistance of the probe cell(s) between the probe cell(s) and its low voltage connection (the common source terminal in the case of MOSFET's). Since the resistor (R.sub.3) is much greater than the cell resistance, the voltage across the resistor is nearly equal to the voltage across the power chip (10). Current probe cells are isolated from switching cells (27) in MOSFET power chips. The cell locations adjacent the probe cells are occupied by cells (50) that are inactive by virtue of their not having had a source region implanted therein during the chip fabrication. This isolation prevents any crosstalk between probe and switching cells.

Abstract: A current limiting circuit wherein a first transistor has an input terminal coupled to a power source, an output terminal coupled to a node which supplies current to the rest of the system, and a control terminal coupled to a source of clock pulses for flowing current from the power source into the node in response to the clock pulses. A second transistor has an input terminal coupled to the power source, an output terminal coupled to the node, and a control terminal coupled to the clock supply and to a current control signal circuit for flowing a second current into the node in response to the clock pulses when a prescribed current control signal is applied to the control terminal. The current which flows through the first transistor is significantly less than the current which flows through the second transistor.

Abstract: A voltage sensing circuit wherein voltages that appear at first and second sensing nodes are converted into first and second currents which are proportional to their respective voltages. A comparing circuit compares the first current to the second current and generates a difference current proportional to the difference between the magnitudes of the two currents. A rectifier circuit rectifies the difference current, and the difference current is added to a reference current. The combined current is applied to the first input terminal of a comparator. The second input terminal of the comparator is coupled to a reference voltage, and the comparator indicates when the voltage created from the combined currents exceeds the reference voltage.

Abstract: A power MOSFET, such as an n-channel MOSFET, is structured to increase the permissible maximum rate of change in voltage during reverse recovery by reducing or eliminating the well containing the active region under the gate bond pad, or any pad which must be isolated from the source metallization, and by providing a polysilicon sheet between the pad area and the substrate. In an n-channel MOSFET where the gate pad is to be protected, the well is a p-well and the active region is the p-region within the well. The p-region under the gate bond pad is reduced to a strip or ring corresponding to the proximity of the gate and the margin of the p-well surrounding the gate pad area. The polysilicon sheet is insulated from the gate pad by a dielectric layer and is held at the potential of the source by connection with the source metallization.

Abstract: A current sensing circuit includes a pair of power devices connected in parallel. The mirror terminal of the first power device is coupled to a small sense resistance, and the mirror terminal of the second power device is connected to a large sense resistance. Each mirror terminal is coupled to its own comparator. Small currents are sensed by the comparator coupled to the mirror terminal of the first power device, and large currents are sensed by the comparator coupled to the mirror terminal of the second power device. If multiple mirror terminals are not available, a large sense resistance may be connected to the mirror terminal of the power device, and a small sense resistance may be selectively connected in parallel with the large resistance to provide low current-sensing capabilities. Accuracy of the device is enhanced by circuitry which minimizes the effect of integrated impedance variation and a variation in the low sense resistances.

Abstract: A monolithic semiconductor device for use in various applications such as lateral and vertical MOS transistors, insulated gate conductivity modulated devices and the like together with a method of manufacturing same. The device includes source, body and drain regions, with the body region including a channel section which is disposed adjacent an insulated gate formed on the surface of the device. The source region includes a central contact area flanked by a pair of body segments which extend up through the source region and which create a resistive path between the source contact area and the channel section. A voltage is developed across the resistive path which tends to maintain a parasitic bipolar transistor formed by the source, body and drain regions in a non-conductive state. A source metallization bridges the two body segments and the intermediate source contact thereby shorting the body region to the source.

Abstract: A monolithic semiconductor device and method of manufacturing same having improved high voltage performance. When the device is in wafer form, a metallization structure is formed over scribe zones which are disposed along the scribe lines which define the edge of each device. The scribe zones are normally not covered with oxide during conventional semiconductor fabrication so that an ohmic contact is formed with semiconductor body. The metal structure includes a peripheral section which extend around the active region of each device and extension sections which extend across the scribe lines and interconnect the peripheral sections. The metal structure clamps the voltage at the edge of each device, both prior and subsequent to wafer breaking, which prevents as depletion region created by a reverse-biased junction from extending to the edge of the device under high voltage conditions. As a result, high voltage performance is improved.