Patents Assigned to JohnsTech International Corporation
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Patent number: 11906576Abstract: A contact assembly for a testing system for testing integrated circuit devices is disclosed. The contact assembly includes a first blade, a second blade, and an elastomer configured to retain the first blade and the second blade. The first blade and the second blade are electrically conductive. The first blade and the second blade are arranged in a cross configuration so that the first blade and the second blade form a substantially X-shape when assembled. The elastomer is at least columnar in part and non-conductive.Type: GrantFiled: April 27, 2022Date of Patent: February 20, 2024Assignee: JOHNSTECH INTERNATIONAL CORPORATIONInventors: Valts Treibergs, Max A. Carideo, David Skodje, Melissa Hasskamp
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Patent number: 11879925Abstract: A test apparatus for testing device under test (DUT) having an antenna located on the DUT is disclosed. The test apparatus includes: a housing, a socket configured to electrically connect the DUT to a load board, a gripper assembly configured to hold the DUT in place, a retractor configured to release the DUT from the gripper assembly, and an alignment plate configured to align the DUT with the socket. The gripper assembly includes a base and an extender, the base is attached to the housing, and the extender is configured to hold the DUT in place. When the retractor is disengaged from the extender, the extender is configured to hold the DUT in place. When the retractor is engaged with the extender, the extender is configured to release the DUT on the alignment plate.Type: GrantFiled: April 14, 2021Date of Patent: January 23, 2024Assignee: Johnstech International CorporationInventors: Mike Andres, David Johnson, Jason Steinblock
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Patent number: 11867752Abstract: A contact assembly for a Kelvin testing system for testing integrated circuit devices is disclosed. The contact assembly includes at least one grouping of blades including a first force blade, a second force blade, a first sense blade, and a second sense blade; an electrical insulation layer disposed between the first force blade and the first sense blade and between the second force blade and the second sense blade; and an elongated elastomer. The elastomer is configured to be retained by the first force blade, the second force blade, the first sense blade, and the second sense blade. Each of the first force blade, the second force blade, the first sense blade, and the second sense blade includes a recess having an opening and sized to receive and retain at least a portion of the elastomer.Type: GrantFiled: April 29, 2022Date of Patent: January 9, 2024Assignee: Johnstech International CorporationInventors: Valts Treibergs, Max A. Carideo, David Skodje, Melissa Hasskamp
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Patent number: 11821943Abstract: A compliant ground block for a testing system for testing integrated circuit devices is disclosed. The compliant ground block includes a plurality of electrically conductive blades in a side by side generally parallel relationship. The blades are configured to be longitudinally slidable with respect to each other. The block also includes an elastomer configured to retain the plurality of blades. Each blade of the plurality of blades includes a first end and a second end opposite to the first end in the longitudinal direction. The plurality of blades is arranged so that the first end of each blade of the plurality of blades is opposite to the first end of an adjacent blade in the longitudinal direction so that the first end of one blade is adjacent the second end of the adjacent blade. The elastomer is at least tubular (e.g., hollow or solid cylindrical) in part and non-conductive.Type: GrantFiled: October 5, 2021Date of Patent: November 21, 2023Assignee: Johnstech International CorporationInventors: Valts Treibergs, Pat Joyal, Leslie Fliegelman, Max A. Carideo
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Patent number: 11802909Abstract: A compliant ground block for a testing system for testing integrated circuit devices is disclosed. The compliant ground block includes a plurality of electrically conductive blade pairs in a side by side generally parallel relationship. Blades in the plurality of blade pairs are configured to be longitudinally slidable with respect to each other. The block also includes at least one elastomer configured to retain the plurality of blade pairs. Each blade pair of the plurality of blade pairs includes a first blade (or a first blade assembly) and a second blade. The first blade (or the first blade assembly) and the second blade are configured to generate scrubbing motions when the device under test is being pressed down on the compliant ground block or is being released from the compliant ground block.Type: GrantFiled: April 5, 2022Date of Patent: October 31, 2023Assignee: Johnstech International CorporationInventor: Max A. Carideo
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Patent number: 11709183Abstract: A high density thin walled test device testing chips/ICs is disclosed. A housing includes a slot for a contact pin and a pair of elastomers. The pin has an arcuate recess to receive part of the elastomer. Likewise the housing includes a channel to receive part of the elastomer. The recess and channel together partially surround the elastomer but not completely to allow shear forces and expansion space for the elastomer as it is compressed by the channel and recess. In addition, a front channel extends from the top surface of the housing toward the bottom surface but leaving a floor to support the elastomer so that it does not warp the housing when compressed. Further, the channel or the recess may include retainers which prevent the elastomer from moving out of position when the pin is in an uncompressed state.Type: GrantFiled: August 31, 2020Date of Patent: July 25, 2023Assignee: Johnstech International CorporationInventors: David T. Skodje, Michael W. Andres, Jeffrey C. Sherry
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Patent number: 11674998Abstract: A contactor assembly for a testing system is disclosed. The assembly includes a contact having a contact tail and a housing having a top surface and a bottom surface. A slot extends through the housing from the top surface to the bottom surface and defines a first inner side wall of the housing and a first inner end wall. The contact is receivable in the slot. The contact tail includes a sloped terminus. A retainer is disposed on the first inner side wall. When the sloped terminus is engaged with the first inner end wall, at least a portion of the retainer overlaps with the contact forming at an overlapping area in a cross-sectional view, thereby preventing removal of the contact from the top side of the housing.Type: GrantFiled: October 1, 2021Date of Patent: June 13, 2023Assignee: Johnstech International CorporationInventors: Bob Chartrand, David Johnson, Brian Sheposh, Mike Andres
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Patent number: 11467183Abstract: A test socket for a device under test (DUT) is disclosed in several embodiments. One embodiment shows a test socket base (16) with apertures (30) for insertion of test pin insert blocks (28). The blocks are inserted top—in or bottom—in and are provided with registration bosses 80 and teeth 92 or other means for maintaining registration. Blocks are provided with dielectric constants to achieve different frequency response relative to other pins. To achieve great EMI and cross talk isolation, the socket may be made of aluminum with hard anodize coating to insulate test pins (32) from the housing.Type: GrantFiled: October 5, 2020Date of Patent: October 11, 2022Assignee: Johnstech International CorporationInventors: Jeffrey Sherry, Joël Erdman
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Patent number: 11360117Abstract: A structure and method for providing a housing which includes a high frequency (HF) connection between a device under test (DUT) having a wave port 20 and a load board via a waveguide structure. The waveguide includes a wave insert 42, a waveguide adapter 24 and a conductive compliant member 40 which maintains bias between the adapter 24 and the DUT HF port 20 while also maintaining an RF shield despite the variable height of the DUT wave port. The adapter may also include a projection 64 which is received in a recess in the waveguide so that the shielding between the waveguide and adapter has full integrity.Type: GrantFiled: June 24, 2020Date of Patent: June 14, 2022Assignee: Johnstech International CorporationInventors: Jeffrey Sherry, Cory Kostuchowski
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Patent number: 11307232Abstract: A structure and method for providing a housing which includes a high frequency (HF or RF) connection between a device under test (DUT) having a waveguide 22. The waveguide includes a wave insert 22, and a conductive compliant member 40 which maintains bias between the adapter/insert 22 and the DUT HF port 20 while also maintaining an RF shield despite the variable height of the DUT waveport. A passage 50 provides an RF connection between the RF port 62 on the DUT and a RF wave guide horn 54. A plurality of transmitting horns 54 can be arranged to transmit to a single receiving horn 154 so that fewer receivers are required to test multiple DUTs in sequence.Type: GrantFiled: February 20, 2020Date of Patent: April 19, 2022Assignee: Johnstech International CorporationInventors: Jeffrey Sherry, Cory Kostuchowski
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Patent number: 11293968Abstract: A testing system and method for testing integrated circuits with radio frequency (RF) antennas is disclosed. The system includes an alignment plate for receiving a device under test (DUT) having an RF transmitting antenna, an enclosure surrounding but separated from the transmitting antenna, a receiving antenna in a telescopic enclosure, and a conversion circuit connected to the receiving antenna. The conversion circuit is configured to convert an RF output from the DUT to a direct current (DC) voltage. The DC voltage is used as a proxy for the RF output to test the DUT. When testing chips with RF ports, the chip or ports are surrounded by the enclosure which is non-radio reflective and includes antennas for receiving RF outputs disbursed around the enclosure, or a single antenna. If multiple receiving antennas are used, sequential testing can also detect directional transmission patterns to confirm that the direction is correctly calibrated.Type: GrantFiled: May 12, 2020Date of Patent: April 5, 2022Assignee: JOHNSTECH INTERNATIONAL CORPORATIONInventor: Jeffrey Sherry
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Patent number: 11209458Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are protected against damage from balls on a DUT by a protective ball guide which includes recesses for receiving part of the ball but prevents the ball from driving the pins beyond a limited range. The ball guide provides fine alignment horizontally and vertically enabling stable electrical performance.Type: GrantFiled: July 27, 2020Date of Patent: December 28, 2021Assignee: JOHNSTECH INTERNATIONAL CORPORATIONInventors: John Nelson, Ranauld Perez, Jeffrey Sherry, Michael Andres, David Johnson
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Patent number: 11183783Abstract: A test socket (14) for a testing an integrated circuit (12) with controlled impedance while maintaining the structural integrity of the test pins (20). The pin (20) can have a sidewall with a thick portion 32 and a thinner portion (30) along the length of the pin. The pin can have projections (42) which provide a standoff from the slot (40). The sidewalls themselves can have projections or lands (60, 61) which extend into the slot and provide stability for the pin (20).Type: GrantFiled: June 15, 2020Date of Patent: November 23, 2021Assignee: Johnstech International CorporationInventors: Jeffrey Sherry, Michael Andres
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Patent number: 11029335Abstract: This disclosure relates to a method of fabrication contact pins 24 used in testing circuit components, typically integrated circuits and the contact pins themselves. It is desirable to selectively radius certain portions of each pin to achieve desired performance of the entire pin. The portion to be radiused is cut to the desire shaped from a blank material. The portion which is not to be radiused is not cut to its final shape from the blank but to a larger shape which includes the material for the final shape. The entire cut portion is then treated to shape tor round all exposed edges. Then the remaining portion of the pin is cut out from the larger blank area which was previously retained, leaving those portions with non-radiused edged.Type: GrantFiled: August 29, 2018Date of Patent: June 8, 2021Assignee: JOHNSTECH INTERNATIONAL CORPORATIONInventors: David Johnson, Michael Andres, Neil Graf, Kenna Pretts
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Patent number: 10928423Abstract: The test system provides an array of test probes. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and flex circuits continue the electrical connection from the probes to a load board. The test probes are bonded to the flex circuits by ring shaped flowable conductive material. The flex circuits are biased against a load board by an elastomeric pad of spaced part conical projections.Type: GrantFiled: September 4, 2018Date of Patent: February 23, 2021Assignee: Johnstech International CorporationInventors: John DeBauche, Dan Campion, Michael Andres, Steve Rott, Jeffrey Sherry, Brian Halvorson, Brian Eshult
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Patent number: 10877090Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.Type: GrantFiled: July 19, 2017Date of Patent: December 29, 2020Assignee: Johnstech International CorporationInventors: John E. Nelson, Jeffrey C. Sherry, Patrick J. Alladio, Russell F. Oberg, Brian Warwick, Gary W. Michalko
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Patent number: 10794933Abstract: A test socket for a device under test (DUT) is disclosed in several embodiments. One embodiment shows a test socket base (16) with apertures (30) for insertion of test pin insert blocks (28). The blocks are inserted top—in or bottom—in and are provided with registration bosses 80 and teeth 92 or other means for maintaining registration. Blocks are provided with dielectric constants to achieve different frequency response relative to other pins. To achieve great EMI and cross talk isolation, the socket may be made of aluminum with hard anodize coating to insulate test pins (32) from the housing.Type: GrantFiled: June 13, 2017Date of Patent: October 6, 2020Assignee: Johnstech International CorporationInventors: Jeffrey Sherry, Joel Erdman
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Patent number: 10761112Abstract: A high density thin walled test device testing chips/ICs is disclosed. A housing includes a slot for a contact pin and a pair of elastomers. The pin has an arcuate recess to receive part of the elastomer. Likewise the housing includes a channel to receive part of the elastomer. The recess and channel together partially surround the elastomer but not completely to allow shear forces and expansion space for the elastomer as it is compressed by the channel and recess. In addition, a front channel extends from the top surface of the housing toward the bottom surface but leaving a floor to support the elastomer so that it does not warp the housing when compressed. Further, the channel or the recess may include retainers which prevent the elastomer from moving out of position when the pin is in an uncompressed state.Type: GrantFiled: September 7, 2018Date of Patent: September 1, 2020Assignee: Johnstech International CorporationInventors: David T. Skodje, Mike W. Andres, Jeffrey C. Sherry
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Patent number: D942290Type: GrantFiled: July 12, 2019Date of Patent: February 1, 2022Assignee: JOHNSTECH INTERNATIONAL CORPORATIONInventor: John Nelson
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Patent number: D1015282Type: GrantFiled: February 1, 2022Date of Patent: February 20, 2024Assignee: Johnstech International CorporationInventor: Valts Treibergs