Patents Assigned to JohnsTech International Corporation
  • Patent number: 11360117
    Abstract: A structure and method for providing a housing which includes a high frequency (HF) connection between a device under test (DUT) having a wave port 20 and a load board via a waveguide structure. The waveguide includes a wave insert 42, a waveguide adapter 24 and a conductive compliant member 40 which maintains bias between the adapter 24 and the DUT HF port 20 while also maintaining an RF shield despite the variable height of the DUT wave port. The adapter may also include a projection 64 which is received in a recess in the waveguide so that the shielding between the waveguide and adapter has full integrity.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: June 14, 2022
    Assignee: Johnstech International Corporation
    Inventors: Jeffrey Sherry, Cory Kostuchowski
  • Patent number: 11307232
    Abstract: A structure and method for providing a housing which includes a high frequency (HF or RF) connection between a device under test (DUT) having a waveguide 22. The waveguide includes a wave insert 22, and a conductive compliant member 40 which maintains bias between the adapter/insert 22 and the DUT HF port 20 while also maintaining an RF shield despite the variable height of the DUT waveport. A passage 50 provides an RF connection between the RF port 62 on the DUT and a RF wave guide horn 54. A plurality of transmitting horns 54 can be arranged to transmit to a single receiving horn 154 so that fewer receivers are required to test multiple DUTs in sequence.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 19, 2022
    Assignee: Johnstech International Corporation
    Inventors: Jeffrey Sherry, Cory Kostuchowski
  • Patent number: 11293968
    Abstract: A testing system and method for testing integrated circuits with radio frequency (RF) antennas is disclosed. The system includes an alignment plate for receiving a device under test (DUT) having an RF transmitting antenna, an enclosure surrounding but separated from the transmitting antenna, a receiving antenna in a telescopic enclosure, and a conversion circuit connected to the receiving antenna. The conversion circuit is configured to convert an RF output from the DUT to a direct current (DC) voltage. The DC voltage is used as a proxy for the RF output to test the DUT. When testing chips with RF ports, the chip or ports are surrounded by the enclosure which is non-radio reflective and includes antennas for receiving RF outputs disbursed around the enclosure, or a single antenna. If multiple receiving antennas are used, sequential testing can also detect directional transmission patterns to confirm that the direction is correctly calibrated.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: April 5, 2022
    Assignee: JOHNSTECH INTERNATIONAL CORPORATION
    Inventor: Jeffrey Sherry
  • Patent number: 11209458
    Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are protected against damage from balls on a DUT by a protective ball guide which includes recesses for receiving part of the ball but prevents the ball from driving the pins beyond a limited range. The ball guide provides fine alignment horizontally and vertically enabling stable electrical performance.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 28, 2021
    Assignee: JOHNSTECH INTERNATIONAL CORPORATION
    Inventors: John Nelson, Ranauld Perez, Jeffrey Sherry, Michael Andres, David Johnson
  • Patent number: 11183783
    Abstract: A test socket (14) for a testing an integrated circuit (12) with controlled impedance while maintaining the structural integrity of the test pins (20). The pin (20) can have a sidewall with a thick portion 32 and a thinner portion (30) along the length of the pin. The pin can have projections (42) which provide a standoff from the slot (40). The sidewalls themselves can have projections or lands (60, 61) which extend into the slot and provide stability for the pin (20).
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 23, 2021
    Assignee: Johnstech International Corporation
    Inventors: Jeffrey Sherry, Michael Andres
  • Patent number: 11029335
    Abstract: This disclosure relates to a method of fabrication contact pins 24 used in testing circuit components, typically integrated circuits and the contact pins themselves. It is desirable to selectively radius certain portions of each pin to achieve desired performance of the entire pin. The portion to be radiused is cut to the desire shaped from a blank material. The portion which is not to be radiused is not cut to its final shape from the blank but to a larger shape which includes the material for the final shape. The entire cut portion is then treated to shape tor round all exposed edges. Then the remaining portion of the pin is cut out from the larger blank area which was previously retained, leaving those portions with non-radiused edged.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 8, 2021
    Assignee: JOHNSTECH INTERNATIONAL CORPORATION
    Inventors: David Johnson, Michael Andres, Neil Graf, Kenna Pretts
  • Patent number: 10928423
    Abstract: The test system provides an array of test probes. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and flex circuits continue the electrical connection from the probes to a load board. The test probes are bonded to the flex circuits by ring shaped flowable conductive material. The flex circuits are biased against a load board by an elastomeric pad of spaced part conical projections.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: February 23, 2021
    Assignee: Johnstech International Corporation
    Inventors: John DeBauche, Dan Campion, Michael Andres, Steve Rott, Jeffrey Sherry, Brian Halvorson, Brian Eshult
  • Patent number: 10877090
    Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: December 29, 2020
    Assignee: Johnstech International Corporation
    Inventors: John E. Nelson, Jeffrey C. Sherry, Patrick J. Alladio, Russell F. Oberg, Brian Warwick, Gary W. Michalko
  • Patent number: 10794933
    Abstract: A test socket for a device under test (DUT) is disclosed in several embodiments. One embodiment shows a test socket base (16) with apertures (30) for insertion of test pin insert blocks (28). The blocks are inserted top—in or bottom—in and are provided with registration bosses 80 and teeth 92 or other means for maintaining registration. Blocks are provided with dielectric constants to achieve different frequency response relative to other pins. To achieve great EMI and cross talk isolation, the socket may be made of aluminum with hard anodize coating to insulate test pins (32) from the housing.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 6, 2020
    Assignee: Johnstech International Corporation
    Inventors: Jeffrey Sherry, Joel Erdman
  • Patent number: 10761112
    Abstract: A high density thin walled test device testing chips/ICs is disclosed. A housing includes a slot for a contact pin and a pair of elastomers. The pin has an arcuate recess to receive part of the elastomer. Likewise the housing includes a channel to receive part of the elastomer. The recess and channel together partially surround the elastomer but not completely to allow shear forces and expansion space for the elastomer as it is compressed by the channel and recess. In addition, a front channel extends from the top surface of the housing toward the bottom surface but leaving a floor to support the elastomer so that it does not warp the housing when compressed. Further, the channel or the recess may include retainers which prevent the elastomer from moving out of position when the pin is in an uncompressed state.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: September 1, 2020
    Assignee: Johnstech International Corporation
    Inventors: David T. Skodje, Mike W. Andres, Jeffrey C. Sherry
  • Patent number: 10725069
    Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are protected against damage from balls on a DUT by a protective ball guide which includes recesses for receiving part of the ball but prevents the ball from driving the pins beyond a limited range. The ball guide provides fine alignment horizontally and vertically enabling stable electrical performance.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: July 28, 2020
    Assignee: JOHNSTECH INTERNATIONAL CORPORATION
    Inventors: John Nelson, Ranauld Perez, Jeffrey Sherry, Michael Andres, David Johnson
  • Patent number: 10698000
    Abstract: A structure and method for providing a housing which includes a high frequency (HF) connection between a device under test (DUT) having a wave port 20 and a load board via a waveguide structure. The waveguide includes a wave insert 42, a waveguide adapter 24 and a conductive compliant member 40 which maintains bias between the adapter 24 and the DUT HF port 20 while also maintaining an RF shield despite the variable height of the DUT wave port. The adapter may also include a projection 64 which is received in a recess in the waveguide so that the shielding between the waveguide and adapter has full integrity.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: June 30, 2020
    Assignee: Johnstech International Corporation
    Inventors: Jeffrey Sherry, Cory Kostuchowski
  • Patent number: 10686269
    Abstract: A test socket (14) for a testing an integrated circuit (12) with controlled impedance while maintaining the structural integrity of the test pins (20). The pin (20) can have a sidewall with a thick portion 32 and a thinner portion (30) along the length of the pin. The pin can have projections (42) which provide a standoff from the slot (40). The sidewalls themselves can have projections or lands (60, 61) which extend into the slot and provide stability for the pin (20).
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: June 16, 2020
    Assignee: JOHNSTECH INTERNATIONAL CORPORATION
    Inventors: Jeffrey Sherry, Michael Andres
  • Patent number: 10551412
    Abstract: A contact for use in a test set which can be mounted to a load board of a tester apparatus. The contact, which serves to electrically connect at least one lead of a device being tested with a corresponding metallic trace on the load board, has a first end defining multiple contact points. As the test pin is rotated about an axis generally perpendicular to a plane defined by the contact, successive contact points are sequentially engaged by a lead of the device being tested. The test pin has a hard stop edge which engages a hard stop wall which limits its rotation movement. The bottom of the pin has a shallow convex curvature preferably with a flat region and the tip of the test pin has a chisel edge.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: February 4, 2020
    Assignee: Johnstech International Corporation
    Inventor: Michael Andres
  • Patent number: 10495688
    Abstract: A test device for manually testing chips/ICs is disclosed. A housing includes a receiver for a device under test (DUT). The DUT must be pressed into the housing to make adequate contact with the test pins in the bottom of the test device. A screw drive presses the DUT into position and a plurality of holes in the turning knob accommodate through-going pins which on one leg extend through the knob and into an interference path of a fixed barrier stop. The extended leg then engages the stop during rotation to end the downward movement of the screw. Adjustment is made by selecting holes where the pins are inserted. Reversing the pins in the hole allows for storage of the pins when not in use.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: December 3, 2019
    Assignee: Johnstech International Corporation
    Inventors: Jose Lopez, Mehdi Attaran
  • Patent number: 10436819
    Abstract: A structure and method of constructing a tip for a contact pin used in IC test housing for testing integrated circuits. As the pin is deflected when the device under test (DUT) pad engaged the tip of the pin, the tip pressure normally increases as the elastomers biasing the pin are engaged. This causes the elastomer supporting the tip to increase pressure. By widening the tip as it rolls, the pressure is maintained more constant. Also, as the top wears, the pressure on the DUT will be reduced. By making the contact area of the tip to DUT smaller as it wears, the pressure can be made more constant.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: October 8, 2019
    Assignee: Johnstech International Corporation
    Inventors: David A. Johnson, John E. Nelson, Jose E. Lopez
  • Patent number: 10401386
    Abstract: A structure and method for providing a contact pin between a device under test (DUT) and a load board which provides upper and lower contact point which are axial aligned is disclosed. The pin has an upper (30) and lower (32) section and a hinge (44/46) in between which allow flex of both upper and lower contact (24/26) which, but the axial alignment can provide a direct replacement for POGO pins but with greater reliability. It also includes a structure and method for removing upper pins 230 by use of a modified hinge 244a.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: September 3, 2019
    Assignee: Johnstech International Corporation
    Inventors: David Johnson, John Nelson, Sarosh Patel, Michael Andres
  • Patent number: 10330702
    Abstract: A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). To prevent rotation of the pins in the pin guide, a walled recess in the bottom of the pin guide engages flanges on the pins. In another embodiment, the pin guide maintains rotational alignment by being fitted around the pin profile or having projections abutting the pin. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 25, 2019
    Assignee: Johnstech International Corporation
    Inventors: Jathan Edwards, Charles Marks, Brian Halvorson
  • Patent number: 10302675
    Abstract: The terminals of a device under test (DUT) are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane with a top facing the device under test, a bottom facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The bottom pins has a lower contact surface which includes an arcuate portion or ridge which increases contact pressure and ablates oxides by the rocking action of ridge when the DUT in inserted.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 28, 2019
    Assignee: Johnstech International Corporation
    Inventors: John E. Nelson, Jeffrey C. Sherry, Brian Warwick, Gary W. Michalko
  • Patent number: D942290
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: February 1, 2022
    Assignee: JOHNSTECH INTERNATIONAL CORPORATION
    Inventor: John Nelson