Abstract: A linear amplifier that comprises a signal input terminal that receives an input signal having a first common mode voltage, a voltage amplifier having a non-inverting input terminal that receives a second common mode voltage, a first and a second input resistance connected in series from the signal input terminal to the inverting input terminal of the voltage amplifier, a feedback resistance connected between the inverting input terminal and the output terminal of the voltage amplifier, and a constant current source. The constant current source supplies a constant current to a middle node between the first and the second input resistances. The constant current generates a voltage drop, which is equal to a difference between the first and the second common mode voltages, across the first input resistance. Accordingly, the common mode voltage of the output signal is directly determined by the second common mode voltage.

Abstract: Various exemplary embodiments of this disclosure provide parallel to serial conversion apparatuses that includes a bit-swapping circuit that generates bit-swapped parallel data by swapping bits of input parallel data, and a parallel to serial conversion circuit that acquires M1 and M2 bits of the bit-swapped parallel data in a first and a second mode, respectively. The parallel to serial conversion circuit generates serial data by arranging the acquired bits of the bit-swapped parallel data in a first specified order in the first mode and in a second specified order in the second mode The bit-swapping circuit swaps the bits of the input parallel data such that the parallel to serial conversion circuit acquires 1st to M1-th and 1st to M2-th bits of the input parallel data in the first and second modes, respectively, and arranges the acquired bits of the input parallel data in the same order.

Abstract: Exemplary receiving apparatus receives serial data that includes contiguous blocks each having M-bit known pattern. The apparatus includes a serial-parallel conversion circuit that arranges bits in the serial data to generates N-bit wide (N<M) parallel data, a register group including a first register that stores a word of the parallel data and second registers to which the word of the parallel data is sequentially shifted and stored, a comparing circuit that compares the known pattern with storage patterns each including M contiguous bits stored in the register group, and a detecting circuit. The detecting circuit detects reception of the serial data if the comparing circuit detects a first match between the known pattern and a first one of the storage patterns, and a second match between the known pattern and a second one of the storage patterns that starts with a specific bit during a specific clock cycle.

Abstract: An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines.

Abstract: An image processing apparatus includes a memory control circuit that stores pixel data in a frame memory, an image processing circuit that processes the pixel data stored in the frame memory, and an output circuit that outputs processed pixel data. The memory control circuit divides the pixel data into upper bit portions and lower bit portions, and a lower bit processing circuit stores the lower bit portions in the frame memory by one of (i) dividing lower bit portion of each of the pixel data into n unit portions and storing corresponding one of n unit portions in the frame memory during each of n successive frame periods, and (ii) dividing pixels constituting each of the frames into n groups and storing the lower bit portions of the pixel data of pixels in corresponding one of n groups in the frame memory during each of n successive frame periods.

Abstract: The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate insulation film is removed to form an opening that exposes an outside area of the active area, which is outside of the central area where a gate electrode will be formed. A shallow grade layer is formed by implanting impurities into an opening with an energy that does not permit penetration of impurity ions through the gate insulation film.

Abstract: An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines.

Abstract: Various exemplary embodiments provide methods of controlling frame memory, memory control circuits, and image processing apparatuses including the memory control circuits. Data representing values of pixels constituting each of a plurality of frames are received in an order of the frames, and data representing values of pixels constituting a previous frame are read from the frame memory and data representing values of pixels constituting a next frame are written to the frame memory. By reading first data representing values of a portion of the pixels constituting the previous frame from the frame memory before receiving of data representing values of pixels constituting the next frame starts, a delay time before starting to output data representing values of pixels of the previous frame can be shortened.

Abstract: Exemplary embodiments of color conversion circuits and color conversion methods convert input color data into output color data. The input color data is positioned in a three-dimensional color space, which is divided into a plurality of unit cubes each having a fixed dimension. The input color data is converted by performing interpolations using conversion coefficients at vertexes of the unit cube within which the input color data is positioned. When the input color data is positioned on a gray axis of the color space, a substitution circuit substitutes some of the conversion coefficients such that the interpolation becomes a linear interpolation. As a result, it is assured that input color data positioned on the gray axis is converted to gray output color data.

Abstract: A switching-type power-supply which enables the switching with little power loss and a method of switching the switching-type power-supply are provided. The switching-type power-supply unit includes a transformer with primary, secondary, winding and control windings, a switch which switches supply of a primary current from a dotted terminal to a non-dotted terminal through the primary winding, a rectifying diode connected the secondary winding, a monitoring signal generation circuit with a diode and a resistor, the diode between GND and a dotted terminal of the control winding, the resistor between GND and a non-dotted terminal of the control winding, the monitoring signal generation circuit generating a monitoring signal at the dotted terminal of the control winding, and a control unit with a zero-point detector and a controller. The zero-point detector monitoring the monitoring signal and supplying a detection signal to the controller.

Abstract: Image processing apparatuses and methods of processing color image data that perform overdrive are provided. The apparatuses include a restoration block that restores R-, G-, and B-element values of respective pixels of previous one of successive frames based on Y-element values of the respective pixels of the previous one of the successive frames and the color image data of a current one of the successive frames. The apparatus further includes a correction block that compares the R-, G-, and B-element values of the respective pixels of the previous one of the successive frames that the restoration block restored and R-, G-, and B-element values of corresponding pixels of the current one of the successive frames and generates the corrected color image data.

Abstract: Time-interleaved analog-to-digital (AD) conversion circuit, which includes first and second AD converters that generate first and second digital signal sequences by converting an analog input signal into first and second digital signals with a first frequency at first and second timings mutually different with each other is disclosed. The AD conversion circuit further includes a FIFO that receives the first and second digital signal sequences, and a correction filter including first and second portions that are supplied with a common clock signal. The correction filter generates a first corrected digital signal sequence by adding the first synchronized digital signal sequence and the second synchronized digital signal sequence passed through the first portion of the correction filter, and a second corrected digital signal sequence by passing the second synchronized digital signal sequence through the second portion of the correction filter.

Abstract: Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment, i) test timing correcting block sets test timing faster than the actual operation timing of a logical circuit to be tested, ii) logical simulation block performs simulation by using delay times of signal paths corrected by adding minimum slack margin, and iii) when the simulation indicates that an end-side flip-flop cannot acquire data after an expected transition of logical value, masking block generates mask data that masks data held in the end-side flip-flop.

Abstract: An exemplary semiconductor integrated circuit is formed on a surface of a semiconductor chip includes a circuit region and a dummy region on the surface of the semiconductor chip. The circuit region includes a plurality of circuit patterns, which form circuit elements of the semiconductor integrated circuit, in a plurality of pattern layers. The dummy region includes a plurality of character dummies, which do not contribute to an operation of the semiconductor integrated circuit. The character dummies have a fixed shape and dimension, and arranged in a character pattern layer selected from the plurality of pattern layers with a fixed pitch. The dummy region further includes an identification sign formed by connecting selected ones of the character dummies chosen from the plurality of the character dummies.

Abstract: Standard cell libraries and methods of designing semiconductor integrated circuits are provided. At least one of delay-adjusting cell data and load-capacitor cell data is stored in the cell library for a specified type standard cell in addition to the standard cell data. The specified type standard cell may be utilized as a delay-adjusting cell or a load-capacitor cell. Accordingly, precise adjustment of delay times during designing a semiconductor integrated circuit is enabled without requiring registering a new standard cell in the cell library. Semiconductor integrated circuits are also provided that are configured to allow precise adjustment of delay times in the semiconductor integrated circuits.

Abstract: In an output driver circuit, a replica circuit includes seventh and eighth transistors corresponding to first and second transistors, respectively, ninth and tenth transistors corresponding to third or fifth, and fourth or sixth transistors in a driver circuit, respectively, and a resistor corresponding to a termination resistor. A reference voltage and a voltage of a node between the ninth transistor and the resistor are input to an operational amplifier, and an output signal of the operational amplifier is input to gates of the first and seventh transistors.

Abstract: An exemplary apparatus for controlling display devices writes pixel data in a buffer in synchronous with an input clock signal. A differential value that represents a change of timing difference between input and output sides is calculated in each of a plurality of frames, and a timing correction based on the differential value calculated during the previous frame is performed within the vertical blanking period. Thereafter, the pixel data is read and output from the buffer to the display device in synchronous with an output clock signal.

Abstract: Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data.

Abstract: Data conversion circuits and methods of data conversion that enable to keep the continuity in the converted data while reducing a required memory capacity are disclosed. An exemplary conversion circuit includes a LUT that stores representative correction values and an interpolation circuit that generates conversion data by interpolating from representative correction values stored in cells of the LUT that surround an address corresponding to the combination of input signal levels. When the cells that surround the address include a pair of adjacent cells arranged along both sides of a diagonal line of the LUT, the interpolation circuit substitutes one of the representative correction values with a substituted representative correction value that indicates an opposite direction and a same amount of correction as indicated by the other one of the representative correction values stored in the adjacent cells, and then generates the conversion data.

Abstract: A semiconductor integrated circuit has an internal circuit having an input terminal connected to a connection terminal, a protection circuit that discharges an over-voltage supplied to the connection terminal to a power line. The protection circuit includes a first discharge circuit connected to the connection terminal, a second discharge circuit connected to the connection terminal and discharges the over-voltage to the power line, and an over-voltage detect circuit that detects a discharge current flowing through the second discharge circuit and generates an over-voltage detect signal when the discharge current is detected. The first discharge circuit is disabled to discharge the over-voltage when the over-voltage detect signal is supplied.