Abstract: A semiconductor integrated circuit having a multilayer wiring structure is provided which includes: a top metal wiring layer (MTOP) including a plurality of top layer power supply wirings and a next-to-top metal wiring layer (MTOP-1) directly below the top metal wiring layer MTOP including a plurality of next-to-top layer power supply wirings. Each of the top layer and the next-to-top layer power supply wirings also includes first potential wirings for supplying a first potential to the circuit elements and second potential wirings for supplying a second potential to the circuit elements. The top layer power supply wirings and the next-to-top layer power supply wirings cross each other and have a top layer insulating film disposed between them. First and second contacts are provided in the insulating film for connecting the first potential wirings and second potential wirings in the top and the next-to-top metal wiring layers with each other.

Abstract: The brightness characteristic detection circuit 1 divides the frame 21 into a plurality of pixel blocks 22, detects average brightness characteristics of respective pixel blocks, and obtains the maximum or minimum brightness value of input image data from the average brightness characteristics of the pixel blocks. Correcting input image data with correction parameters set in accordance with the detected maximum or minimum brightness value generates display data. Even if a noise is incorporated in the image data, the influence of the noise is suppressed and the image data may be processed accurately.

Abstract: A method and an apparatus for driving passive matrix liquid crystal, comprising the steps of: simultaneously selecting Y row electrodes, where Y is an odd number of 7 and above; calculating an exclusive OR between a Y-bit row selection vector representing a selection pattern of the Y row electrodes and Y-bit ON/OFF display data representing a display pattern of column electrodes, for each corresponding bit; adding the exclusive ORs for each bit; when X=(Y+1)/2, and a 1/(X?1) voltage of the maximum voltage of the column electrodes is Vc, selecting a voltage level of the column electrodes from X voltage levels satisfying:[2×i?(X?1)]×Vc (i=an integer of 0 to (X?1)) in accordance with the result of the addition for driving. These method and apparatus prevent the frame response phenomenon of high-speed liquid crystal while realizing high-contrast display, low-voltage driving, low power consumption, and reduction in chip size.

Abstract: An exemplary cell library includes a first plurality of types of standard cells. Each of the first plurality of types of standard cells includes threshold voltage adjusting patterns. The upper and the lower boundaries of the threshold voltage adjusting patterns contact the upper and lower boundaries of the cell frame and the distances between the left and right boundaries of the-threshold voltage adjusting patterns and the cell frame are set appropriately. Accordingly, it is possible to place standard cells including transistors with different threshold voltages at arbitrary positions without increasing the area of a circuit block or the design cost.

Abstract: The method of manufacturing a crystal oscillator that is compensated for temperature with low-cost, and a crystal oscillator that is compensated for temperature by the method is disclosed. A plurality of crystal oscillators are manufactured by preparing a compensation circuit that generates a common compensation voltage in accordance with a predetermined compensation curve expressed by a quintic polynomial of an ambient temperature; and manufacturing each of the plurality of crystal oscillators by integrating the compensation circuit with a voltage controlled oscillation circuit including a crystal resonator, the common compensation voltage generated by the compensation circuit being supplied to the voltage controlled oscillation circuit so that the temperature characteristic of the crystal resonator is compensated.

Abstract: A method of designing a logic circuit including pass transistors is disclosed. A logic group having a complementary variable in a given logical expression to be realized into the logic circuit is mapped using a multiplexer composed of a combination of the pass transistors. The number of transistors used in the logic circuit and the number of stages can be reduced by taking advantage of the multiplexer. When a logic circuit including both pass transistors and a multiple-input logic gate is designed, a logic group having a common variable in the given logical expression is mapped using the multiple-input logic gate. The number of transistors used in the logic circuit and the number of stages can be further reduced by taking advantage of the multiple-input logic gate. In order to ease the above mapping procedure, a complementary variable is identified and the given logical expression is optimized by grouping product terms of the logical expression by the complementary variable.

Abstract: Not only an instantaneous pilot symbol value resulting from correcting a phase of one demodulated pilot symbol in response to phase deviation of the one pilot symbol but also a pilot symbol value resulting from correcting a phase of the same pilot symbol corresponding to the instantaneous pilot symbol value in response to averaged phase deviation of a plurality of demodulated receive pilot symbols is calculated. Further, weight factors are generated on the basis of a difference between the instantaneous pilot symbol value and the pilot symbol value, and the respective demodulated receive data is weighted by using the weight factors to combine the receive data.

Abstract: A plurality of standard cells 10 are arranged to form a channel-less standard cell array 1, which has vertical and horizontal sides. A plurality of first proximity dummy cells 20 are arranged along each of the vertical sides of the standard cell array to form a first proximity dummy bands 20 such that the upper and lower sides of the first proximity dummy cells are in contact with each other and such that the left or right side of each of the first proximity dummy cells is in contact with the vertical side of the standard cell array 1. Furthermore, a plurality of second proximity dummy bands are arranged along each of the horizontal sides of the standard cell array to form a second proximity dummy bands such that the upper or lower side of each of the second proximity dummy cells is in contact with the horizontal side of the standard cell 1.

Abstract: A high accuracy D/A converter includes D/A converter sections including 64 current cells for outputting a current corresponding to 1 LSB of 8-bit input data and a D/A converter section including 63 current cells, a reference current generating section for supplying the respective D/A converter sections with reference currents, and a decoder for activating each of the current cells from the D/A converter sections to the D/A converter section in the stated order in a cyclic manner when the 8-bit input data value is increased, and deactivating one each of the activated current cells from the D/A converter section to the D/A converter section in the stated order in a cyclic manner when the 8-bit input data value is decreased.

Abstract: A communication system for transmitting and receiving data at high speed can be self-tested at actual operating speed with low cost, and without increasing the chip area. A test signal generation unit generates test parallel data. A transmitter for test purpose converts the parallel data into serial data. A selector selectively supplies the serial data output from the transmitter to a receiver during a test operation. The receiver converts the serial data into parallel data. After that, a detector detects an error in the parallel data output from the receiver. In this case, only the transmitter is disposed in correspondence with receivers. Serial data output from the transmitters is supplied to the receivers through the selector.

Abstract: A method of designing a logic circuit including pass transistors is disclosed. A logic group having a complementary variable in a given logical expression to be realized into the logic circuit is mapped using a multiplexer composed of a combination of the pass transistors. The number of transistors used in the logic circuit and the number of stages can be reduced by taking advantage of the multiplexer. When a logic circuit including both pass transistors and a multiple-input logic gate is designed, a logic group having a common variable in the given logical expression is mapped using the multiple-input logic gate. The number of transistors used in the logic circuit and the number of stages can be further reduced by taking advantage of the multiple-input logic gate. In order to ease the above mapping procedure, a complementary variable is identified and the given logical expression is optimized by grouping product terms of the logical expression by the complementary variable.

Abstract: A semiconductor device includes an internal circuit having a data holding circuit, and at least one leakage current cut-off circuit provided between the internal circuit and a power supply or a ground, and is capable of preventing data in the data holding circuit from being destroyed. A ground-side cut-off circuit includes a switch and a control circuit. The switch electrically connects or cuts a path between a source of a ground-side transistor of the internal circuit and the ground. The control circuit turns off the switch upon detecting that source potential of the ground-side transistor is substantially equal to that of the ground. Upon detecting that the source potential of the ground-side transistor rises to a predetermined potential lower than a potential necessary for holding the data in the data holding circuit, the control circuit turns on the switch.

Abstract: Manufacturing equipment performs different processes, including a first process that produces a reaction products and a second process that removes the reaction products, in a same chamber. The amount of reaction products in the chamber is monitored, and a priority order between the first and the second processes is set based on the monitored amount of the reaction products. The order of the first and the second processes is determined based on the set priority order. The amount of reaction products can be kept within an acceptable range without performing a long-period lot-to-lot cleaning, and a high manufacturing efficiency is realized.

Abstract: A semiconductor integrated circuit includes a phase-locked loop (PLL) circuit configured to generate an oscillation output signal synchronized with a reference clock and a plurality of clock and data recovery (CDR) circuits configured to adjust a phase of the oscillation output signal and a phase of serial data. The PLL circuit converts a voltage output from a loop filter, the voltage functioning to control an oscillation frequency of an oscillator, into a current and delivers the converted current to the plurality of CDR circuits. Therefore, in a case where clock signals used in a plurality of serial transmission channels are synchronized with one another, limitations on layout of clock wiring from the PLL circuit to the CDR circuits and the occurrence of jitter are reduced.

Abstract: The present invention relates to a de-spreading method and a de-spreading apparatus, in which an correlation operation between input signals time-sequentially inputted and a predetermined code is performed so that data suitable for the code is extracted from the input signals. An object of the present invention is to reduce the circuit scale and the dissipation power. The de-spreading apparatus has a delay circuit for delaying the input signal relatively with respect to the synchronization detecting code to generate a delay signal, and an correlation circuit (the arithmetic operating unit 183, the adder 184, the registers 186E, 186P and 186L, etc.) for performing three correlation operations (Early), (Punctual) and (Late) between the input signal or the delay signal selected in accordance with the three correlation operations E, P and L, and the synchronization detecting code on a time division basis.

Abstract: An anti-fuse is manufactured by forming an isolation region including an insulating material layer buried in a surface of a device formation region on a surface of a semiconductor substrate, and by forming diffusion regions at both sides of the isolation region, then by contacting electrodes to the respective diffusion regions. The anti-fuse is initially in a non-conductive state, and is programmed to be in a permanently conductive state by a simple writing circuit.

Abstract: A semiconductor integrated circuit that has an output circuit in which an output-stage operating voltage lower than a power supply voltage is applied to an output stage is provided. Even when the power supply voltage is lowered, a sufficient output signal amplitude can be obtained. An increase in circuit scale can be prevented and the power consumption can be reduced. An output-stage operating voltage supply source, including an N-channel MOS transistor having a first threshold voltage, applies an operating voltage lower than a power supply voltage to the output stage of the output circuit. A drive-circuit operating voltage supply source, including an N-channel MOS transistor having a second threshold voltage lower than the first threshold voltage, applies a drive-circuit operating voltage higher than the output-stage operating voltage to a drive circuit.

Abstract: A lock-detection circuit that can set an acceptable phase-error range adapted to define a locked state and/or an unlocked state at a constant rate without being affected by a frequency and that can detect the locked state and/or the unlocked state with precision without being affected by various fluctuations and variations, and a PLL circuit including the lock-detection circuit. The range corresponding to a phase difference between first and second output signals is determined to be a locked-state range, where the phase of each of the first and second output signals delays or advances with reference to that of an oscillation-output signal transmitted from a voltage-controlled-oscillation circuit.

Abstract: A overdrive circuit and a liquid crystal display panel driving apparatus that can overdrive the display panel with a high accuracy without requiring a large memory capacity or a complicated arithmetic circuit is disclosed. The overdrive circuit includes a basic look-up table (LUT) that outputs a basic overdrive amount, and a temperature coefficient LUT that outputs a temperature coefficient of the overdrive amount. The overdrive circuit generates a corrected overdrive amount using the basic overdrive amount and the temperature coefficient.

Abstract: A semiconductor integrated circuit that includes a circuit element with a reduced parasitic capacitance and has a short start-up time. A well of the different type of conduction from that of the substrate is formed in the area of the surface of the semiconductor substrate under the circuit element. A constant voltage, which biases the junction between the well and the semiconductor substrate in a reverse direction, is applied to the well through a resistor having a higher impedance compared with the impedance of the capacitance of the reverse-biased junction between the well and the substrate at the frequency of the signal applied to the circuit element.