Abstract: Plasma processing apparatus and plasma processing methods capable of maintaining etching characteristics and to prevent degradation of a lower electrode even when the focus ring is severely eroded by the plasma are disclosed. According to an exemplary embodiment, a side-surface protecting ring formed of a ceramic material having an erosion rate by the plasma lower than an erosion rate of the material of the focus ring is provided to cover the side surface of the lower electrode. As a result, it becomes possible to prevent the side surface of the lower electrode from being exposed to the plasma and maintain the etching characteristics even after the focus ring is severely eroded. Further, degradation of the lower electrode is decreased.

Abstract: The configuration of a CAM device can be set in various manners depending on a system in which CAM having different configurations is needed. The CAM device includes a CAM array including a plurality of physical banks, a logical bank-physical bank converter for setting the assignment between logical banks and physical banks, and for outputting a control signal to set the configuration of a physical bank assigned to the logical bank, depending on a logical bank signal indicating a logical bank to be searched, a priority circuit for outputting search results in accordance with predetermined priority, and a cascade circuit for performing a logical operation on the search results output from the priority circuit of the present CAM device and a search results supplied from a higher-order CAM device, and transmitting the results of the logical operation to a lower-order CAM device.

Abstract: A timing detection circuit including a first timing detection circuit, a second detection circuit, and an output circuit is disclosed. The first detection circuit detects, among multiphase clocks having n mutually different phases and a frequency of k times the frequency of a reference clock, a closest clock having a clock edge closest to a valid edge of the synchronizing signal and generates first detect signal DET_A indicating the detected clock. The second timing detection circuit detects within which of k successive cycles of the representative clock selected from the multiphase clocks the valid edge of the synchronizing signal is positioned and generates second detect signal DET_B indicating the detected cycle. The output circuit receives the first detect signal and the second detect signal and outputs first output signal OUT_A and second output signal OUT_B.

Abstract: A cyclic orthogonal matrix with three rows and four columns is used to drive a simple-matrix liquid crystal panel. Three gradation palettes having different phases of ON/OFF data of intermediate gradations are generated. A frame-rate-control phase table for an entire screen of the liquid crystal panel is generated in which the three gradation palettes are distributed so that the sequence direction of the ON/OFF data of the three gradation palettes coincides with the circulation direction of data of the cyclic orthogonal matrix, and a predetermined gradation palette is assigned to each pixel of the liquid crystal panel. Frames of the frame-rate-control gradation system and column vectors of the cyclic orthogonal matrix are simultaneously updated field-by-field to perform drive control and gradation control of each pixel of the liquid crystal panel. The gradation display of each pixel of the liquid crystal panel is completed for 12 fields constituting the three frames of the frame-rate-control gradation system.

Abstract: A lock-detection circuit that can set an acceptable phase-error range adapted to define a locked state and/or an unlocked state at a constant rate without being affected by a frequency and that can detect the locked state and/or the unlocked state with precision without being affected by various fluctuations and variations, and a PLL circuit including the lock-detection circuit. The range corresponding to a phase difference between first and second output signals is determined to be a locked-state range, where the phase of each of the first and second output signals delays or advances with reference to that of an oscillation-output signal transmitted from a voltage-controlled-oscillation circuit.

Abstract: A semiconductor integrated circuit includes a phase-locked loop (PLL) circuit configured to generate an oscillation output signal synchronized with a reference clock and a plurality of clock and data recovery (CDR) circuits configured to adjust a phase of the oscillation output signal and a phase of serial data. The PLL circuit converts a voltage output from a loop filter, the voltage functioning to control an oscillation frequency of an oscillator, into a current and delivers the converted current to the plurality of CDR circuits. Therefore, in a case where clock signals used in a plurality of serial transmission channels are synchronized with one another, limitations on layout of clock wiring from the PLL circuit to the CDR circuits and the occurrence of jitter are reduced.

Abstract: In a data transmission system, a transmitter encodes n-bit transmit data into m-bit code (2n>m>n), and simultaneously transmits the encoded m-bit code via m signal lines. A receiver receives the m-bit code transmitted from the transmitter via the m signal lines, and decodes the received m-bit code into an n-bit data thereby obtaining received data. In the transmitter, the n-bit transmit data is encoded into an m-bit code in accordance with predefined one-to-one correspondence between 2n codes with a width of n bits and 2n codes with a width of m bits each including equal or similar number of “1”s and “0”s selected from 2m codes with the width of m bits, and amplitude levels of transmitted signals are adjusted such that the average voltage of the m signal lines is maintained constant.

Abstract: A method of operating a semiconductor integrated circuit including a SRAM block, in which non-volatile data is stored in the SRAM block, is disclosed. In an exemplary embodiment, the non-volatile data is stored by flowing a drain current in one of a pair of pull-down transistors constituting the SRAM cell while supplying a fixed potential to the sources of the pull-down transistors. A semiconductor integrated circuit including a SRAM block and a control circuit that controls the SRAM block to store non-volatile data is also disclosed.

Abstract: A semiconductor device that prevents a build-up of electrostatic charge in a dummy pad is provided. The semiconductor device may contain an internal circuit formed on a semiconductor substrate and the dummy pad which is not electrically connected to the internal circuit. The semiconductor device may further include a seal ring that surrounds the internal circuit and the dummy pad, where the seal ring is electrically connected to the semiconductor substrate and includes a pattern in a first metal layer, a contact between the pattern in the first metal layer and the semiconductor substrate, patterns in upper metal layers stacked above the pattern in the first metal layer, and multiple electrical contacts between the patterns in the first metal layer and the upper metal layers, in which the dummy pad is electrically connected to the seal ring.

Abstract: An output buffer circuit, which minimizes or prevents output delay of output signal and degradation of slew rate while suppressing overshoot and undershoot, is provided. In a first time period when an input signal to a gate of an N-channel output transistor changes from ‘L’ level to ‘H’ level, the gate is connected to an output terminal through a capacitor element so that the overshoot is suppressed. In addition, the output buffer circuit stores negligible electrical charge in the capacitor element prior to the first time period, which results in minimal delay in outputting a buffered signal and degradation of slew rate while suppressing undershoot when the input signal changes from ‘H’ level to ‘L’ level in the first time period.

Abstract: A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.

Abstract: A method of manufacturing a display device capable of maintaining a cell gap constant is provided. The method includes forming a plurality of columnar spacers on a substrate on which a plurality of pixel electrodes are formed; forming a coating material film with a flat upper surface on the substrate so that heads of the columnar spacers protrude from the flat upper surface of the film of the coating material; and polishing the protruded heads of the columnar spacers using the flat upper surface of the coating material as a reference surface until the top faces of the columnar spacers are flush with the flat upper surface of the film of the coating material.

Abstract: A high accuracy D/A converter includes D/A converter sections including 64 current cells for outputting a current corresponding to 1 LSB of 8-bit input data and a D/A converter section including 63 current cells, a reference current generating section for supplying the respective D/A converter sections with reference currents, and a decoder for activating each of the current cells from the D/A converter sections to the D/A converter section in the stated order in a cyclic manner when the 8-bit input data value is increased, and deactivating one each of the activated current cells from the D/A converter section to the D/A converter section in the stated order in a cyclic manner when the 8-bit input data value is decreased.

Abstract: In an exemplary layout structure of a semiconductor integrated circuit manufactured by a photolithographic process using an exposing light having a wavelength ?, a peripheral circuit region is formed by arranging a plurality of peripheral circuit cells, each having peripheral circuit patterns, along a side of an internal circuit region. A proximity dummy region is formed by arranging a plurality of proximity dummy cells, each having a proximity dummy pattern, along at least one side of the peripheral circuit region. The proximity dummy region includes a line-and-space repetition structure including, and having the regularity of, two or more pairs of lines and spaces between the lines every 8?. The repetition structure in the proximity dummy region reduces the dimensional deviation in the outermost portion of the peripheral circuit region.

Abstract: A content addressable memory includes a plurality of word memories which respectively have assigned addresses, and each outputs a match/mismatch signal representing storage or no storage of a data item matching search data in a search mode, a priority encoder which output addresses of word memories which output the match signals in the search mode in predetermined fixed priority order, a first prior word-memory setting section for setting a first prior word memory, and a priority changing part which masks the match signals output from upper-positional word memories of the word memories, which correspond to word memories having upper positions compared with the first prior word memory in the fixed priority order in the priority encoder, and transmits signals representing that the word memories having the upper positions output no match signals to the priority encoder.

Abstract: The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate insulation film is removed to form an opening that exposes an outside area of the active area, which is outside of the central area where a gate electrode will be formed. A shallow grade layer is formed by implanting impurities into an opening with an energy that does not permit penetration of impurity ions through the gate insulation film.

Abstract: A RAKE receiver device includes a plurality of fingers for demodulating multipath receive data, and a data synthesis circuit for synthesizing the receive data from each of the paths and demodulated by the plural fingers. Each time the receive data is demodulated by one of the plural fingers, the data synthesis circuit adds cumulatively the demodulated receive data for each identical receive data from each of the paths, and synthesizes the data.

Abstract: A system debugging device in which, even if bus ownership is transferred to other bus masters, the operations of the other bus masters can be monitored such that efficient debugging of a system can be achieved is provided. In a system where a plurality of bus masters mounted on an LSI share a bus, the system debugging device includes a recorder for recording a variety of information including master selection information for specifying a bus master to which a right to use the bus is granted and slave selection information for selecting a bus slave specified according to address signals outputted from the bus master; and a reader for reading, via the bus, the variety of information recorded in the recorder.

Abstract: The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate insulation film is removed to form an opening that exposes an outside area of the active area, which is outside of the central area where a gate electrode will be formed. A shallow grade layer is formed by implanting impurities into an opening with an energy that does not permit penetration of impurity ions through the gate insulation film.

Abstract: A semiconductor integrated circuit that has an output circuit in which an output-stage operating voltage lower than a power supply voltage is applied to an output stage is provided. Even when the power supply voltage is lowered, a sufficient output signal amplitude can be obtained. An increase in circuit scale can be prevented and the power consumption can be reduced. An output-stage operating voltage supply source, including an N-channel MOS transistor having a first threshold voltage, applies an operating voltage lower than a power supply voltage to the output stage of the output circuit. A drive-circuit operating voltage supply source, including an N-channel MOS transistor having a second threshold voltage lower than the first threshold voltage, applies a drive-circuit operating voltage higher than the output-stage operating voltage to a drive circuit.