Abstract: In a data transmission system, a transmitter encodes n-bit transmit data into m-bit code (2n>m>n), and simultaneously transmits the encoded m-bit code via m signal lines. A receiver receives the m-bit code transmitted from the transmitter via the m signal lines, and decodes the received m-bit code into an n-bit data thereby obtaining received data. In the transmitter, the n-bit transmit data is encoded into an m-bit code in accordance with predefined one-to-one correspondence between 2n codes with a width of n bits and 2n codes with a width of m bits each including equal or similar number of “1”s and “0”s selected from 2m codes with the width of m bits, and amplitude levels of transmitted signals are adjusted such that the average voltage of the m signal lines is maintained constant.

Abstract: A clock generating circuit includes a delay circuit which has input terminals and which delays a signal input from each of the input terminals by a different delay time, and outputs the delayed signal from at least one output terminal, a selective circuit which receives an input clock signal and selectively outputs the clock signal to one of the input terminals of the delay circuit, and a control circuit which switches selective operations of the selective circuit. A modulated clock signal in which the period of the clock signal is increased or decreased is output from the at least one output terminal of the delay circuit such that the control circuit sequentially switches the selective operations of the selective circuit.

Abstract: A data transfer apparatus includes at least one master and a plurality of slaves connected by a ring-connection bus, and a controller having a master port and slave ports connected to the corresponding master and slaves, respectively. In such a ring-like structure, a large amount of data can be transferred efficiently, and even if data continuously flows on the bus, data transfer is performed in a master/slave structure, thereby reducing the overall data transfer time.

Abstract: The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate insulation film is removed to form an opening that exposes an outside area of the active area, which is outside of the central area where a gate electrode will be formed. A shallow grade layer is formed by implanting impurities into an opening with an energy that does not permit penetration of impurity ions through the gate insulation film.

Abstract: An object of the present invention is to provide an oscillator contributing to a reduction of power dissipation. An oscillator 10 comprises four inductors 11—1, 11—3, 11—2, and 11—4 connected in series to constitute a closed circuit, and four capacitors 12—1, 12—3, 12—2, and 12—4 one ends of which are connected to nodes that are connecting points of the inductors, and another ends of which are held at a power supply VDD. The oscillator 10 is formed on a semiconductor substrate.

Abstract: A serial data link, which derives an incoming data clock linked to the data rate of the incoming data, also generates an outgoing data clock that is used to re-transmit the data from the serial link into the communications channel. The incoming and outgoing data clocks are derived from a single local oscillator, using dual phase interpolating circuits to adjust the phase lead/lag to match the incoming data rate.

Abstract: A multi-layered film on a semiconductor substrate is etched with a multi-step etching process by sequentially providing a plurality of process gases having different compositions in a chamber. A plasma discharge to excite the process gases is continued without an interruption during a switch to a different process gas. A relationship between different process gases desirable for the continuous plasma excitation is also disclosed. An apparatus suitable to practice this continuous plasma excitation process includes a process gas supply system having a gas reservoir. A mixture of at least two component gases is prepared and reserved in the reservoir, and is supplied to the etching chamber when it is needed.

Abstract: A phase detector that compares the phases of data and four-phase first to fourth clocks having a half rate of the data and being 90° out of phase with one another. Exemplary embodiments of the phase detector include first to fourth sampling circuits that sample the data by the four-phase first to fourth clocks; a first comparator that compares sampling data obtained by sampling according to the adjacent two-phase first and second clocks using the first and second sampling circuits, respectively, and when the sampling data is different, outputs a first up signal; and a second comparator that compares sampling data obtained by sampling according to the adjacent two-phase fourth and first clocks using the fourth and first sampling circuits, respectively, and when the sampling data is different, outputs a first down signal.

Abstract: An over-sampling circuit is provided at a front stage of a digital matched filter, and a received signal is over-sampled with it. Synchronous acquisition of the received spread spectrum signal is implemented by adding the data obtained by the over-sampling, inputting it into the digital matched filter, and then performing a correlation thereon.

Abstract: Data conversion circuits and methods of data conversion that enable to keep the continuity in the converted data while reducing a required memory capacity are disclosed. An exemplary conversion circuit includes a LUT that stores representative correction values and an interpolation circuit that generates conversion data by interpolating from representative correction values stored in cells of the LUT that surround an address corresponding to the combination of input signal levels. When the cells that surround the address include a pair of adjacent cells arranged along both sides of a diagonal line of the LUT, the interpolation circuit substitutes one of the representative correction values with a substituted representative correction value that indicates an opposite direction and a same amount of correction as indicated by the other one of the representative correction values stored in the adjacent cells, and then generates the conversion data.

Abstract: A wiring structure for effectively reducing wiring capacitance, and a method of forming the wiring structure is disclosed. An underlying film having a dielectric constant lower than that of silicon oxide is formed on at least side surfaces of the wires of a wiring layer and a low dielectric constant film having an even lower dielectric constant is formed between the wires. Further, the surfaces of the underlying film are positively sloped. Because the low dielectric constants of the underlying film and the low dielectric constant film, wiring capacitance is effectively reduced. Further, the positively sloped surfaces facilitate the filling of narrow spaces between the wires by the low dielectric constant film.

Abstract: A method and an apparatus for driving passive matrix liquid crystal, comprising the steps of: simultaneously selecting Y row electrodes, where Y is an odd number of 7 and above; calculating an exclusive OR between a Y-bit row selection vector representing a selection pattern of the Y row electrodes and Y-bit ON/OFF display data representing a display pattern of column electrodes, for each corresponding bit; adding the exclusive ORs for each bit; when X=(Y+1)/2, and a 1/(X?1) voltage of the maximum voltage of the column electrodes is Vc, selecting a voltage level of the column electrodes from X voltage levels satisfying: [2×i?(X?1)]×Vc (i=an integer of 0 to (X?1)) in accordance with the result of the addition for driving. These method and apparatus prevent the frame response phenomenon of high-speed liquid crystal while realizing high-contrast display, low-voltage driving, low power consumption, and reduction in chip size.

Abstract: A method and an apparatus for driving passive matrix liquid crystal, comprising the steps of: simultaneously selecting Y row electrodes, where Y is an odd number of 7 and above; calculating an exclusive OR between a Y-bit row selection vector representing a selection pattern of the Y row electrodes and Y-bit ON/OFF display data representing a display pattern of column electrodes, for each corresponding bit; adding the exclusive ORs for each bit; when X=(Y+1)/2, and a 1/(X?1) voltage of the maximum voltage of the column electrodes is Vc, selecting a voltage level of the column electrodes from X voltage levels satisfying: [2×i?(X×1)]×Vc (i=an integer of 0 to (X?1)) in accordance with the result of the addition for driving. These method and apparatus prevent the frame response phenomenon of high-speed liquid crystal while realizing high-contrast display, low-voltage driving, low power consumption, and reduction in chip size.

Abstract: An error correction circuit and a folding ADC are provided. In the folding ADC, the range of the input voltage to an upper ADC circuit and to a lower ADC circuit is shifted by a predetermined voltage toward higher and lower electric potential sides. The error correction circuit outputs the conversion result of the upper bits as is, or corrects the conversion result of the upper bits by either subtracting or adding 1 from or to the conversion result of the upper bits in accordance with the least significant bit within the conversion result of the upper bits and in accordance with the polarity of a code having different polarities between a period in which the voltage level of one folding signal among a plurality of folding signals output from the folding circuit is higher than the center level and a period in which the voltage level is lower.

Abstract: A protocol translation cable assembly includes a first connector having a first plurality of pins, a second connector having a second plurality of pins, and an electrical cable coupling the first connector to the second connector, where the electrical cable includes a plurality of conductors. The protocol translation cable assembly further includes translation circuitry coupled to at least some of the plurality of wires of the electric cable at points between the first plurality of pins of the first connector and the second plurality of pins of the second connector. The translation circuitry preferably derives its power from the electrical cable such that separate power supplies are not required. The cable assembly therefore provides transparent “plug-and-play” capabilities.

Abstract: Exemplary semiconductor integrated circuits are disclosed that include polysilicon fuses that can be programmed by supplying programming currents. The fuse is formed of a polysilicon film having a sheet resistance of 1.7 to 6 k?/sq. As a result, the polysilicon fuse has a high resistance and can be programmed with low current. Accordingly, the fuse can be programmed with a high yield even when the programming current is supplied through a wire having a high resistance.

Abstract: A wiring structure to effectively reduce the wiring capacitance, and a method of forming the wiring structure is disclosed. In one embodiment, an underlying film having a dielectric constant than that of silicon oxide is formed on at least on side surfaces of the wires of a wiring layer and a low dielectric constant film having a further lower dielectric constant is formed between the wires. Further the surfaces of the underlying film are positively sloped. Because the low dielectric constants of the underlying film and the low dielectric constant film, the wiring capacitance is effectively reduced. Further, the positively sloped surfaces facilitate the filling of narrow spaces between the wires by the low dielectric constant film.

Abstract: A method of operating a semiconductor integrated circuit including a SRAM block, in which non-volatile data is stored in the SRAM block, is disclosed. In an exemplary embodiment, the non-volatile data is stored by flowing a drain current in one of a pair of pull-down transistors constituting the SRAM cell while supplying a fixed potential to the sources of the pull-down transistors. A semiconductor integrated circuit including a SRAM block and a control circuit that controls the SRAM block to store non-volatile data is also disclosed.

Abstract: Plasma processing apparatus and plasma processing methods capable of maintaining acceptable etching characteristics and to prevent degradation of a lower electrode even when the focus ring is severely eroded by the plasma, while leaving the plasma discharge conditions used in the conventional apparatus and methods substantially unchanged, are disclosed. According to an exemplary embodiment, a side-surface protecting ring formed of a ceramic material is provided to cover the side surface of the lower electrode such that an outer perimeter of the side-surface protecting ring is approximately aligned with, or inside, an outer perimeter of the substrate to be processed. As a result, the side-surface protecting ring does not influence the plasma characteristic.

Abstract: A CMOS image sensor includes a plurality of pixel sensors arranged in a two-dimensional array. In each pixel sensor, a signal corresponding to the absolute value of the amount of incident light with reduced reset noise is obtained. The signals of the respective pixel sensors are then output in a block scanning fashion. The CMOS image sensor does not need to include a preprocessing circuit for discrete cosine transform or a high-capacity frame memory for raster scanning.