Patents Assigned to Kinsus Interconnect Technology
  • Patent number: 10039185
    Abstract: Provided is a landless multilayer circuit board and a manufacturing method thereof. The manufacturing method includes steps of forming a first circuit on a first substrate, patterning a photoresist layer to form at least one via between the first circuit and a second circuit, forming at least one connecting pillar in the at least one via, removing the photoresist layer, forming a second substrate to cover the at least one connect pillar, and forming the second circuit on the second substrate. The second circuit is connected to the first circuit through the at least one connecting pillar. When the second circuit is formed, the at least one via does not need to be filled, thereby making the second circuit flat.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: July 31, 2018
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nong Lin
  • Publication number: 20180160533
    Abstract: A multilayer printed circuit board includes a first circuit board, a second circuit board and bonding films. The first circuit board includes a first dielectric layer, a first wiring pattern layer, a plurality of conductive blocks and a plurality of solder balls. The first wiring pattern layer is formed on a first surface of the first dielectric layer and the conductive blocks are formed on a second surface of the first dielectric layer. The solder balls are formed on a surface of the first wiring pattern layer. The second circuit board includes a second dielectric layer, a second wiring pattern layer, second conductive blocks and conductive pillars. The second wiring pattern layer is formed on a third surface of the second dielectric layer and the second conductive blocks are formed on a fourth surface thereof. The conductive pillars are formed on the second wiring pattern layer.
    Type: Application
    Filed: December 5, 2016
    Publication date: June 7, 2018
    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao LIN, Chiao-Cheng CHANG, Yi-Nong LIN
  • Patent number: 9967975
    Abstract: A multi-layer circuit board includes a first circuit board, multiple conducting blocks, a second circuit board, and multiple conducting recesses. The first circuit board has a first conductor layer formed thereon. The conducting blocks are mounted on the first circuit board and electrically connected to the first conductor layer. The second circuit board has a second conductor layer mounted thereon and facing the first circuit board. The conducting recesses are formed in the surface of the second circuit board. Each conducting recess has a conducting layer electrically connected to the second conductor layer. When the conducting blocks are mounted in the conducting recesses, the first conductor layer and the second conductor layer are electrically connected through the conducting blocks and the conducting recesses. As can be separated from the first circuit board for test of the two conductor layers, the yield of the second circuit board is enhanced.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: May 8, 2018
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nong Lin
  • Patent number: 9901016
    Abstract: An EMI shielding device is provided. A first shielding layer is formed on a first surface of a first substrate, and a first through hole is formed through the first substrate. A second substrate is mounted in an opening of the first through hole, and a second shielding layer is formed on a surface of the second substrate. A conductive paste is mounted between the first substrate and the at least one second substrate to electrically connected the first shielding layer and the second shielding layer. A protective layer, an antirust layer, and a shielding layer are sequentially mounted on the conductive paste. The EMI shielding device is mounted on a printed circuit board (PCB) by Surface Mount Technology. Therefore, the EMI shielding device may be firmly mounted on the PCB, and there is not any narrow gap that may leak electromagnetic radiation.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: February 20, 2018
    Assignee: Kinsus Interconnect Technology Corp.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yung-Lin Chia
  • Patent number: 9847165
    Abstract: A winged coil structure and a method of manufacturing the same are disclosed. The winged coil structure includes an upper flexible plate, at least one upper magnetic induction coil, at least one upper connection pad, a lower flexible plate, at least one lower magnetic induction coil, at least one lower connection pad, at least one gold finger, a dielectric layer and at least one connection plug. The connection plug connects the upper connection pad and the lower connection pad through thermal pressing such that the gold finger, the upper magnetic induction coil, the upper connection pad, the lower connection pad, the connection plug, the lower connection pad and the lower magnetic induction coil are electrically connected. The upper flexible plate is provided with notched lines to be easily bent without damage to the upper and lower magnetic induction coils. Thus, a bendable feature for magnetic induction coils is provided.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: December 19, 2017
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nong Lin
  • Patent number: 9831167
    Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with an opening bonded to a carrier board in order to form a compound carrier board structure. A die is placed in the opening and bonded to the carrier board. A sealant is filled in a gap between surrounding walls of the opening and the die at a height lower than the die to fixedly place the die within the opening and to leave a non-active surface of the die exposed.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: November 28, 2017
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Yi-Fan Kao, Shuo-Hsun Chang, Yu-Te Lu, Kuo-Chun Huang
  • Patent number: 9754870
    Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with a penetrating rectangular opening bonded to a non-conductive film then a carrier board in order to form a compound carrier board structure. The baseplate is constructed with a low Thermal Expansion Coefficient material.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: September 5, 2017
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Yi-Fan Kao, Shuo-Hsun Chang, Yu-Te Lu, Kuo-Chun Huang
  • Patent number: 9744624
    Abstract: Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 ?m for fine line width/pitch.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: August 29, 2017
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Jaen-Don Lan, Pin-Chung Lin, Chen-Rui Tseng, Cheng-En Ho, Yu-An Chen
  • Patent number: 9570227
    Abstract: Disclosed is a magnetic excitation coil structure including a magnetic coil sheet formed of a thin film and rolled as a cylindrical body with a hollow hole, and an insulation layer covering the outer surface of the cylindrical body formed by the magnetic coil sheet for protection. The magnetic coil sheet includes a flexible substrate, a dielectric layer attached to the flexible substrate, and a plurality of patterned circuit layers embedded in the flexible substrate and in contact with the dielectric layer. Each patterned circuit layer is separate, and the upper surfaces of the patterned circuit layers and the upper surface of the flexible substrate form a co-plane. The magnetic coil structure provides an electrical function of coil, which is enhanced by the patterned circuit layer due to its high aspect ratio of the electrical circuit, thereby greatly increasing the whole magnetic flux and electromagnetic effect.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: February 14, 2017
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nong Lin
  • Patent number: 9439292
    Abstract: A method for manufacturing a circuit board with a buried element having high density pin count, wherein a micro copper window formed in a first circuit by patterned dry film electroplating is easily controlled less than 50 ?m so that the micro conduction holes formed after the laser drilling each has a diameter greatly shrunk less than 50 ?m so as to highly increase density of the micro conduction holes, thereby facilitating in burial of the buried element with the high density pin count. Additionally, by disposing the micro conduction holes in the same elevation, optically aligning a fixing position for the buried element can be controlled precisely.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: September 6, 2016
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Yi-Fan Kao, Jaen-Don Lan, Yung-Lin Chia, An-Ping Tseng
  • Patent number: 9439290
    Abstract: A carrier board structure includes at least one upper magnetic coil, at least one lower magnetic coil, a flexible board, a dielectric layer, at least one connection pad and at least one gold finger. The flexible board has a middle region having a middle hole, and two side regions thinner than the middle region. A groove used as a fold line is provided on the lower surface of each side region bordering on the middle region. The upper and lower magnetic coils are configured in the flexible board and separated by the dielectric layer. The gold fingers are provided on the two side regions and connected to the upper magnetic coils. The upper and lower magnetic coils are around the middle hole and connected by the connection pads. The fold lines help the two side regions to fold without damage to the upper and lower magnetic coils.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: September 6, 2016
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nong Lin
  • Patent number: 9406641
    Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate having a flip region with a through-opening and bonding to a Non-conductive Film to bond to a carrier board in order to form a compound carrier board structure. The baseplate is constructed with a low Thermal Expansion Coefficient material.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: August 2, 2016
    Assignee: Kinsus Interconnect Technology Corp.
    Inventors: Ting-Hao Lin, Yi-Fan Kao, Shuo-Hsun Chang, Yu-Te Lu, Kuo-Chun Huang
  • Patent number: 9370110
    Abstract: A method of manufacturing a multilayer substrate structure includes the steps of pre-treatment, pressing and post-treatment. A carrier plate provided with a circuit pattern layer is pressed against a plastic sheet. An interlayer connection pad is formed by drilling and filling the lower surface of the plastic sheet. The carrier plate, the plastic sheet, another plastic sheet and another carrier plate with a circuit pattern layer are pressed together, and then drilled/filled to form a multilayer stacked structure such that the two circuit pattern layers are indirectly and electrically connected to the interlayer connection pad, respectively. Therefore, it is possible to overcome the problem due to alignment tolerance by using the interlayer connection pad wider than alignment tolerance, and stacking the circuit layers, each having much finer line and smaller pitch.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: June 14, 2016
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Yu-Te Lu
  • Patent number: 9351409
    Abstract: A method of manufacturing a thin support package structure includes the steps of: preparing a support plate formed with a plurality of grooves adjacent to an outer rim thereof, forming a releasing material layer on the support plate; forming a first circuit layer on the releasing material layer so as to form a thin circuit board; forming a dielectric layer on the releasing material layer; forming a plurality of openings in the dielectric layer; forming a second circuit layer on the dielectric layer; forming connection plugs by filling the openings; forming a solder mask on the dielectric layer; forming a plurality of notches on the lower surface of the support plate to communicate with the grooves, respectively; and removing the central part of the support plate between the notches and the central part of the releasing material layer on the support plate.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: May 24, 2016
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Hsueh-Ping Chien, Jun-Chung Hsu
  • Patent number: 9301405
    Abstract: A method for manufacturing microthrough-hole includes electroplating a metal layer on a carrier plate, patterning the metal layer to form a first circuit having copper pads, covering the first circuit with a photoresist layer and not covering the copper window between two of the copper pads, etching the metal layer beneath the copper window and removing the photoresist layer, sequentially forming an insulation layer and a second circuit on the first circuit and the copper window, the second circuit layer having a stop pad corresponding to the copper window, removing the carrier plate, upward drilling through the insulation layer between the stop pad and the copper window to form a microthrough-hole beneath the stop pad, and forming a conductive layer in the microthrough-hole to form the microthrough-hole connecting the first and second circuits. The microthrough-hole and its occupied area is greatly reduced, thereby achieving high circuit density.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: March 29, 2016
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Yi-Fan Kao, Jaen-Don Lan, Yu-Te Lu, Yung-Lin Chia, An-Ping Tseng
  • Patent number: 9198296
    Abstract: A double sided board with buried element and a method for manufacturing the same are disclosed. At least one buried element is fixed on a dielectric layer and embedded in an insulation layer. First and second electrical circuits are formed on upper and lower surfaces of the insulation layer, respectively. At least one through-hole is formed in the insulation layer and filled with a conductive layer to electrically connect the first and the second electrical circuits. The dielectric layer beneath the buried element and the insulation layer above the buried element are provided with at least one opening, respectively, which is filled with the conductive layer, thereby connecting the conductive layer and external circuits or electrical elements. Additionally, the first and second electrical circuits are covered with first and second solder masks, respectively, so as to avoid environmental effect and improve preciseness of the circuits.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: November 24, 2015
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Yu-Te Lu, Fu-Song Chen
  • Publication number: 20150282306
    Abstract: A multilayer substrate structure includes a first plastic sheet, a second plastic sheet, a first circuit pattern layer, a second circuit pattern layer, and an interlayer connection pad. A first connection plug connected to the interlayer connection pad fills in a first opening of a first plastic sheet and is connected to a first connection pad of the first circuit pattern layer. A second connection plug fills a second opening of the second plastic sheet and is connected to a second connection pad of the second circuit pattern layer such that the second circuit pattern layer is electrically connected to the first circuit pattern layer via the interlayer connection pad. Therefore, even if there is little offset, it is possible to overcome the alignment tolerance and assure electrical connection between the circuit layers as desired.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 1, 2015
    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Yu-Te Lu
  • Publication number: 20150282333
    Abstract: A method of manufacturing a multilayer substrate structure includes the steps of pre-treatment, pressing and post-treatment. A carrier plate provided with a circuit pattern layer is pressed against a plastic sheet. An interlayer connection pad is formed by drilling and filling the lower surface of the plastic sheet. The carrier plate, the plastic sheet, another plastic sheet and another carrier plate with a circuit pattern layer are pressed together, and then drilled/filled to form a multilayer stacked structure such that the two circuit pattern layers are indirectly and electrically connected to the interlayer connection pad, respectively. Therefore, it is possible to overcome the problem due to alignment tolerance by using the interlayer connection pad wider than alignment tolerance, and stacking the circuit layers, each having much finer line and smaller pitch.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 1, 2015
    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Yu-Te Lu
  • Publication number: 20150271915
    Abstract: An enhanced chip board package structure includes a chip board and a plurality of enhanced structures, which are formed in the blind openings of the non-effective region of the chip board. Each enhanced structure has an opening. The mechanical strength is reinforced by the enhanced structures without changing the whole thickness so as to overcome the problem of warping. Meanwhile, the three-dimensional stability is thus enhanced. The opening of the enhanced structure can be selectively filled with the filler such that the mechanical strength is further reinforced and the thermally conductive effect is greatly improved.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 24, 2015
    Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Jun-Chung Hsu, Bo-Yu Tseng, Yu-Hsiang Sun
  • Patent number: 9095084
    Abstract: A stacked multilayer structure, including a first circuit layer having bumps, a plastic film stacked on the first circuit layer to fill up the space among the bumps so as to form a co-plane, and a second circuit layer formed on the co-plane and connected to the first circuit layer. The plastic film includes a glass fiber layer which is embedded and not exposed.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: July 28, 2015
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Yu-Te Lu, De-Hao Lu