Abstract: Embedded passive device structure and its manufacturing method for mainly embedding the passive device structure in the printed circuit board are presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased.

Abstract: A method for fabricating an IC board without a ring structure is provided. In the method, after the completion of the core board (including the core through hole), the second pattern photoresist layer is used to mask over the first deposited metal layer, and a portion of the second deposited metal layer (this portion of the second deposited metal layer is to electrically couple to the conductive circuit of the core through hole). Later, the second deposited metal layer, the first deposited metal layer, the metal layer, and the substrate at the innermost layer which are not masked by the second pattern photoresist layer are removed. As a result, the substrate is exposed to form the ringless structure, and to couple a conductive line to the core board through hole.

Abstract: An electroplating method by transmitting electric current from a ball side is provided. In the electroplating method, the circuit layer is firstly formed on the bump side of the IC board, and the electric current is transmitted to the portion of the circuit layer uncovered by the insulating layer formed on the bump side from the electroplated metal layer on the ball side to form the protective layer (the electroplated gold layer) on the portion of the circuit layer. In such a way, the electroplated gold layer cannot be formed under the insulating layer formed on the bump side (attached with the chip) because the electroplated gold layer is formed after the insulating layer has been formed, and thereby the fall-off of the insulating layer from the electroplated gold layer will not happen. Therefore, the reliability of the products is enhanced.

Abstract: A method for manufacturing coreless substrates is provided herein. The method first provides a base whose top and bottom sides are covered with metal layers respectively that are detachable from the base. From the two metal layers, the method then develops the bump-pad side or ball side wiring layers required by the coreless substrate simultaneously. The two metal layers along with their respective wiring layers are then separated from the base into two independent semi-products of the coreless substrate. The method then develops from the other sides of the two semi-products the laminate side wiring layers required by the coreless substrate.

Abstract: The present invention relates to a Fine Pitch flip chip substrate. A black oxide dam is made on the metal circuit between bump pads to replace the conventional solder resist so that the bump pads will not be buried in the solder resist. A small via is drilled by laser drilling and plated filled with copper to be used as the connection between the circuits. By this way, the density and the flexibility of routing could be improved. A mesh pattern can be made in the limited space to increase the stiffness of the substrate.

Abstract: A method for a manufacturing process of micro bump pitch IC substrates uses a dielectric layer to replace the conventional solder resist, then uses CCD high precision alignment laser drill to open up the defined bump pad lands, and fills them with via plating filled metal accompanied by etching to enlarge the bump pads, and finally plates the bum pads with Sn/Pb. This can simultaneously solve the problems of insufficient strength of bump pads, limitation of printing technology and being unable to apply the solder in the conventional technologies. The method can provide a higher packaging density, higher yield rate, and provides a total solution to the next generation high density IC design.