Patents Assigned to L3 Communication
  • Patent number: 10186059
    Abstract: Embodiments are directed to representing radio frequency (RF) signals in a visualization using particle bursts. In one scenario, a computer system instantiates RF signal sources in a virtualization, where each RF signal source is configured to emit RF signals. The computer system then generates a stream of particle bursts to represent at least one of the emitted RF signals, and provides a visualization that shows the instantiated RF signal sources along with the generated particle bursts representing the emitted RF signals. In some cases, the visualization may be used to illustrate an anti-access, aerial denial (A2AD) environment. In other cases, the visualization may be used to illustrate network communications using particles, where each particle represents network data packets.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: January 22, 2019
    Assignee: L3 Communications Corp.
    Inventors: Adrian Musters, Thomas R. Giallorenzi, Joseph J. Booker, Joe M. Brown, Dimitri Negroponte, Sam Leventer, Clinton B. Hope
  • Publication number: 20140159994
    Abstract: An integrated dual-mode visual display system which includes both a large-area heads down display and a heads up display combined in a single unit includes a housing or chassis, a flat panel display attached to the housing or chassis, a HUD projector for projecting HUD images and/or data, and a processor housed within the housing or attached to the chassis for driving both the HUD projector and the flat panel display. The processor comprises a video generator for generating video images to be displayed on the flat panel display and on the HUD. The HUD and the HDD (the flat panel display) can display the same information, completely distinct information, or information that has some commonality (some information is uniquely displayed on one or the other of the HUD and HDD displays, while some information is displayed on both the HUD and the HDD).
    Type: Application
    Filed: December 4, 2013
    Publication date: June 12, 2014
    Applicant: L3 Communications Corporation
    Inventor: Joseph H. GARCIA
  • Patent number: 8751990
    Abstract: A system for determining the median of a plurality of data values comprises a plurality of field programmable gate arrays (FPGA), a plurality of inter FPGA links, an input router, a plurality of median modules, and a plurality of output transfer modules. Each FPGA includes a plurality of configurable logic elements and configurable storage elements from which the other components are formed. The inter FPGA link allows communication from one FPGA to another. The input router receives the plurality of data values and creates a plurality of data streams. The median module receives at least one data stream, increments a plurality of counters corresponding to a single data value within the range of data values, and determines the median by accumulating the contents of each counter. The output transfer module transfers the median to an external destination along with performance statistics of the determination of the median.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: June 10, 2014
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Matthew R. Standfield, Jim D. Allen, Juan Esteban Flores, Michael O'Neal Fox, Deepak Prasanna, Matthew P. DeLaquil
  • Patent number: 8677489
    Abstract: Methods, apparatus, and computer readable storage media reduce or eliminate network traffic meeting criteria. In some aspects, network traffic transmitted by one or more source nodes to one or more destination nodes may comprise a denial of service attack against the destination node(s). At least a portion of the denial of service attack traffic may be reduced or eliminated with the disclosed methods and apparatus. In one aspect, a method of managing undesirable network traffic transmitted from a source node to a destination node over a communications network includes receiving a notification of a routing rule change, authenticating the notification, determining a network routing rule based on the notification, applying the network routing rule, determining a network path toward the source node, determining an entity based on the network path, and transmitting a notification of the routing rule change to the entity.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: March 18, 2014
    Assignee: L3 Communications Corporation
    Inventors: Matthew Strebe, Timothy C. Collins, Nathan V. Whittenton
  • Patent number: 8583720
    Abstract: A method for using a system to compute a solution to a partial differential equation (PDE) broadly comprises the steps of determining the true accuracy required (TAR) to solve the PDE, determining an architecture according to the TAR that performs a plurality of calculations to solve the PDE, determining a time allowed (TA) and a time required (TR) based on the architecture to solve the PDE, rejecting the PDE if the TR is less than or equal to the TA, configuring a plurality of programmable devices with the architecture, initiating the calculations, and ceasing the calculations when an accuracy criteria is met or when the TA expires. The system broadly comprises a plurality of programmable devices, a plurality of storage elements, a device bus, a plurality of printed circuit (PC) boards, and a board to board bus.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: November 12, 2013
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Antone Kusmanoff, Matthew P. DeLaquil, Deepak Prasanna, Jerry W. Yancey
  • Patent number: 8375395
    Abstract: A computing architecture comprises a plurality of processing elements to perform data processing calculations, a plurality of memory elements to store the data processing results, and a reconfigurable interconnect network to couple the processing elements to the memory elements. The reconfigurable interconnect network includes a switching element, a control element, a plurality of processor interface units, a plurality of memory interface units, and a plurality of application control units. In various embodiments, the processing elements and the interconnect network may be implemented in a field-programmable gate array.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: February 12, 2013
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Deepak Prasanna, Matthew Pascal DeLaquil
  • Patent number: 8258959
    Abstract: An environmentally sealed electronic device with an internal activation circuit that does not require a constant interrogation signal to maintain power to its internal circuitry. The electronic device includes sensor circuitry for gathering or sensing data; an internal battery for powering the sensor circuitry; and an internal activation circuit for activating the sensor circuitry. The sensor circuitry may include a temperature sensor, a location sensor, a signal sensor, a sound detector, a motion sensor, or any other device that senses or gathers data. The battery may be any type of energy storage device such as a lithium or alkaline battery. The activation circuit includes a receiver for receiving a radio frequency signal from an external source and a switch for connecting the battery to the sensor circuitry in response to the receiver. The switch is operable to maintain connection of the battery to the sensor circuitry after the radio frequency signal ceases.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: September 4, 2012
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventor: Joshua D. Anderson
  • Patent number: 8255011
    Abstract: A mobile communication device includes a processor; a data acquisition device for acquiring data and providing it to the processor; a transceiver for transmitting at least some of the acquired data to an external device; and a low-power clock. The low-power clock counts down a random delay time period and temporarily shifts the processor and the transceiver from low-power sleep modes to active wake modes so that the processor and transceiver can transmit at least some of the acquired data to the external device while in their active wake modes.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: August 28, 2012
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Bryan Lloyd Westcott, Scott Burkart
  • Publication number: 20120194556
    Abstract: The present invention provides a system and method for displaying exocentric views of an aircraft in a three-dimensional manner, wherein a pilot, or other user, can select from a plurality of different exocentric viewpoints. The user can thus see a three-dimensional rendering of the terrain, obstacles, and/or other images around the aircraft from vantage points other than the egocentric vantage point of most aircraft display systems. This enables the pilot to easily increase his or her situational awareness.
    Type: Application
    Filed: January 24, 2012
    Publication date: August 2, 2012
    Applicant: L3 Communications Avionics Systems, Inc.
    Inventors: John M. Schmitt, Jonathan A. Price
  • Patent number: 8188919
    Abstract: A system and method for estimating a geolocation of a non-cooperative target using any reasonable target location estimate. Collectors may acquire actual signal measurements including a direction of arrival (DOA), a target range, a time difference of arrival (TDOA), a range rate, a range sum, and/or a frequency difference of arrival (FDOA). A processing device may receive the actual signal measurements and navigational data regarding the collectors. Then, the processing device may calculate an estimated target location as a solution to a nonlinear optimization problem where an objective function to be minimized is a weighted sum-of-squares of differences between the actual signal measurements and calculated values corresponding to signal measurements that theoretically should be produced for a particular target location. The algorithm used to solve this problem may be a globally convergent algorithm, such as a Levenberg-Marquardt algorithm.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: May 29, 2012
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Michael T. Grabbe, Bryan Lloyd Westcott
  • Patent number: 8175095
    Abstract: Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Dynamically-sized data packets, sized in accordance with the amount of data ready to be sent, are transferred between the devices and/or interfaces on the card.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: May 8, 2012
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Joshua D. Anderson, Scott M. Burkart, Matthew P. DeLaquil, Deepak Prasanna
  • Patent number: 8166090
    Abstract: A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate a first product, and a first linear solver module for calculating an updated first element of the vector variable using the first product. A second circuit includes a second multiplication module for multiplying a second row of the matrix by a second instance of the vector variable to generate a second product, and a second linear solver module for calculating an updated second element of the vector variable using the second product. An interface module updates the second instance of the vector variable with the first updated element, and updates the first instance of the vector variable with the second updated element.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: April 24, 2012
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Matthew Pascal DeLaquil, Deepak Prasanna, Scott Michael Burkart, Joshua D. Anderson, Antone Lee Kusmanoff
  • Patent number: 8149975
    Abstract: A system for identifying at least one phase transition in a phase-shift keying signal comprising a plurality of data samples corresponding to phase values. The system comprises a memory operable to store computing device executable instructions; and a computing device. The computing device is operable to generate a first falling edge region function for each data sample; generate a first rising edge function for each data sample; generate a first level function for each data sample; and generate a second falling edge function for each data sample. The second falling edge function equals the first falling edge function if the first falling edge function is greater than the first rising edge function and the first level function, and the second falling edge function equals zero.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: April 3, 2012
    Assignee: L3 Communications Integrated Systems L.P.
    Inventor: Stephen Ha
  • Patent number: 8139864
    Abstract: A system for correcting image characteristic data from a plurality of pixels comprises at least one field programmable gate array (FPGA), a lookup table, and a correction module. The FPGA may include a plurality of configurable logic elements and a plurality of configurable storage elements. The lookup table may be accessible by the FPGA and may store a plurality of correction components associated with each pixel, including a gain value, an offset value, and a bad pixel value. The correction module may be formed from the configurable logic elements and configurable storage elements and may receive the characteristic data and the correction components. The correction module may generate corrected data for each characteristic data by utilizing the gain value, the offset value, and the bad pixel value.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: March 20, 2012
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Matthew R. Standfield, Jim D. Allen, Michael O'Neal Fox, Deepak Prasanna, Matthew P. DeLaquil
  • Patent number: 8065356
    Abstract: A programmable element for data processing comprises a crosspoint switch (318), a mathematical operation module (320), and a plurality of data hold modules (604,606). Each of the data hold modules (604,606) receives data from the crosspoint switch (318) and communicates the data to an input of the mathematical operation module (320) such that data arrives at the inputs of the mathematical operation module (320) substantially simultaneously. A first data hold module (604) communicates a first data valid signal to a second data hold module (606) upon receipt of first valid data, and the second data hold module communicates a second data valid signal to the first data hold module upon receipt of second valid data.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: November 22, 2011
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Jerry William Yancey, Yea Zong Kuo
  • Patent number: 8032763
    Abstract: A Personal Computer Memory Card International Association (PCMCIA) card is disclosed. The PCMCIA card may include a cryptographic module, a communications interface, and a processor. The cryptographic module may perform Type 1 encryption of data received from a computer into which the card is inserted. The cryptographic module may support High Assurance Internet Protocol Encryption (HAIPE). The communications interface may provide connectivity to a network adapter. The communications interface may include a Universal Serial Bus (USB) interface. The processor may detect whether a network adapter is coupled to the communications interface, identify a device driver that corresponds to the network adapter, and employ the device driver to provide operative communication between the cryptographic module and the network adapter. The PCMCIA card may contain a datastore that maintains a plurality device drivers. For example, the plurality of device drivers support any one of IEEE 802.x, Ethernet, V.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: October 4, 2011
    Assignee: L3 Communications Corporation
    Inventors: John A. Modica, Kenneth White
  • Patent number: 8001167
    Abstract: An automatic background noise estimator (BNE) seed calculator for determining a starting point for a BNE circuit which tracks the noise floor received by a receiver. The BNE seed calculator may sample a plurality of data points from the receiver and calculate the magnitude of each point. The seed calculator may then determine the peak magnitude value, a plurality of mean values, and the variance of the sampled points. A plurality of lookup tables are used to compare the peak, mean, and variance values with simulated peak, mean, and variance values to estimate the noise floor level of the actual signal and use that to determine the optimum BNE seed value. Simulation software such as MATLAB is used to develop the lookup tables by simulating peak, mean, and variance values based on a plurality of signal-to-noise ratios (SNR).
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: August 16, 2011
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Mark Allen Chivers, Sujit Ravindran
  • Patent number: 7984293
    Abstract: A Personal Computer Memory Card International Association (PCMCIA) card may establish, via a non-secure network, a secure communications channel between a computer and a secure network. The non-secure network may define a first address space. The secure network may define a second address space. The PCMCIA card may include a cryptography module, a network adapter, and/or a processor. The cryptography module may provide Type 1 cryptography of data communicated between the computer and the secure network. The network adapter may be in communication with the non-secure network and may be associated with a first network address from the first address space. The processor may be in communication with the secure network via the cryptography module and the network adapter. The processor may identify a second network address for the computer from the second address space and may communicate the second network address to the computer, for example via dynamic host control protocol (DHCP).
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: July 19, 2011
    Assignee: L3 Communications Corporation
    Inventor: Richard Norman Winslow
  • Publication number: 20110153706
    Abstract: A fast Fourier transform (FFT) architecture operable to transform data of variable point size includes a plurality of input ports, a plurality of memory elements, a crosspoint switch, a plurality of processing elements, and a plurality of output ports. The inputs ports read time-domain data from an external source. The memory elements store input data, intermediate calculation results, and output data. The crosspoint switch allows data to flow from any one architecture component to any other architecture component. The processing elements perform the FFT calculation. The output ports write frequency-domain data to an external source.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 23, 2011
    Applicant: L3 Communications Integrated Systems, L.P.
    Inventor: Jerry William Yancey
  • Patent number: 7946284
    Abstract: An apparatus for covertly marking a target includes a housing sized and configured to simulate a portable electronic device; a reservoir positioned in the housing for holding a quantity of miniature markers; and a dispersing mechanism positioned in or on the housing for dispersing the markers onto the target.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: May 24, 2011
    Assignee: L3 Communications Integrated Systems, L.P.
    Inventors: Matthew P. DeLaquil, Thomas J. Galli