Abstract: A system for characterizing a compressed sensing apparatus is described which broadly includes a random vector generator for generating an input vector, a waveform generator in communication with the random vector generator for converting the input vector into an analog signal, a compressed sensing apparatus in communication with the digital-to-analog converter for determining a digital bit stream from the analog signal, a serial-to-parallel converter for converting the digital bit stream into an input vector; and an electronic processor in communication with the random number generator and the serial-to-parallel converter configured for determining a compressed sensing matrix.

Abstract: Provided is a programmable matrix element or “PME” (which may be part of an ASIC central processing unit) operable to manipulate a data set of real and complex numbers derived from an input signal. Specific operations may include: addition, subtraction, multiplication, accumulation, storage and scaling. Each PME includes a plurality of multi-stage signal processing modules, which may be two-staged modules. Each state, in turn, includes: at least one data manipulation module for manipulating the input signal; a crosspoint switch for facilitating the receipt and parallel distribution of an input signal/manipulated output signal; and a programmable control module operable to support data manipulation by controlling manipulation functions, storing data and routing signals. A given crosspoint switch may be programmed to interconnect data manipulation modules in “datapipe” fashion, which is to say via a specified number of parallel data pathways.

Abstract: A system for sorting data and calculating statistics on large data sets with a known value range includes a memory element and a processing element configured to execute steps of the methods. Methods for sorting data include establishing an array of counters such that each counter corresponds to a value in the data set, reading the numbers and incrementing the counter corresponding to the value of each number, and listing the values in sequential order wherein each value occurs in the list according to the count of the corresponding counter. Methods for calculating statistics utilize the count stored in each counter from the sorted data and the value that corresponds thereto.

Abstract: A system for evaluating the convergence to a solution for a matrix equation comprises at least one reconfigurable computing device such as a field programmable gate array (FPGA), an update storage element, a conversion element, a summation unit, and a comparator. The FPGA includes a plurality of configurable logic elements and a plurality of configurable storage elements, which are utilized to form the update storage element, the conversion element, the summation unit, and the comparator. The update storage element is configured to store a plurality of updates. The conversion element determines the absolute value of the updates. The summation unit accumulates the absolute values of the updates to produce a total sum, which is compared to a convergence factor by the comparator. Convergence is signaled when the total sum is less than the convergence factor.

Abstract: An apparatus for covertly marking a target includes a housing sized and configured to simulate a portable electronic device; a reservoir positioned in the housing for holding a quantity of miniature markers; and a dispersing mechanism positioned in or on the housing for dispersing the markers onto the target.

Abstract: A system for characterizing a compressed sensing apparatus is described which broadly includes a random vector generator for generating an input vector, a waveform generator in communication with the random vector generator for converting the input vector into an analog signal, a compressed sensing apparatus in communication with the digital-to-analog converter for determining a digital bit stream from the analog signal, a serial-to-parallel converter for converting the digital bit stream into an input vector; and an electronic processor in communication with the random number generator and the serial-to-parallel converter configured for determining a compressed sensing matrix.

Abstract: A system for a conjugate gradient iterative linear solver that calculates the solution to a matrix equation comprises a plurality of gamma processing elements, a plurality of direction vector processing elements, a plurality of x-vector processing elements, an alpha processing element, and a beta processing element. The gamma processing elements may receive an A-matrix and a direction vector, and may calculate a q-vector and a gamma scalar. The direction vector processing elements may receive a beta scalar and a residual vector, and may calculate the direction vector. The x-vector processing elements may receive an alpha scalar, the direction vector, and the q-vector, and may calculate an x-vector and the residual vector. The alpha processing element may receive the gamma scalar and a delta scalar, and may calculate the alpha scalar. The beta processing element may receive the residual vector, and may calculate the delta scalar and the beta scalar.

Abstract: An integrated circuit in communication with a host circuit includes an interconnect bus and a plurality of programmable elements. Each of the programmable elements includes a control interface for receiving a control signal, the control signal causing the memory element to selectively operate in one of a plurality of modes. In a first mode, the memory element communicates stored data to the output port upon receiving the control signal; in a second mode the memory element communicates stored data to the output port upon detecting valid data at the input port; in a third mode the memory element stores a first data value consisting of at least a portion of a single data word received at the input port; and in a fourth mode the memory element stores a second data value consisting of at least a portion of each of two separate input values received at the input port. Each programmable element may write data to and read data from a memory element of any of the other programmable elements.

Abstract: An improved PDA-like portable electronic communication device includes a housing having a display screen on the front and a mounting surface that is contoured to generally conform to the shape of a user's forearm. In this way, the communication device can be comfortably and securely worn on a user's forearm so that it is constantly or immediately available for use. In example embodiments, the mounting surface is formed by the back side of the housing and is cylindrically concave or frustoconically concave. In other example embodiments, the device includes a mount to which the housing attaches in multiple positions, with the mount having a frustoconically concave back surface in one embodiment and with another embodiment additionally including mating cylindrically convex and concave surfaces of the mount and the housing.

Abstract: The present invention is a method and computer program for equalizing group delay and magnitude of a system for which a system response is known. The method and computer program are implemented via a finite impulse response (“FIR”) filter for the system, and the method broadly comprises the steps of: evaluating a desired response for the system as a function of an amplitude of the system and a phase of the system; separating the phase of the system into a linear component and a non-linear component; performing a first optimization by minimizing a weighted error between a desired response for the system and a cascaded response for the system as a function of an equalizing filter and a phase slope so as to obtain at least one local smallest error E(?) as a function of phase slope; and once the local smallest error E(?) is known, performing a second optimization to locate any existing global smallest error, wherein the global smallest error is within a set distance from the local smallest error.

Abstract: A mobile communication device includes a processor; a data acquisition device for acquiring data and providing it to the processor; a transceiver for transmitting at least some of the acquired data to an external device; and a low-power clock. The low-power clock counts down a random delay time period and temporarily shifts the processor and the transceiver from low-power sleep modes to active wake modes so that the processor and transceiver can transmit at least some of the acquired data to the external device while in their active wake modes.

Abstract: A system and method for symbol rate estimation using vector velocity that does not require any prior knowledge of the signal's structure and is accurate in the presence of frequency offset and noise. An input signal is converted to a symbol constellation path signal, and a velocity signal representing a velocity of the symbol constellation path signal is generated. A first frequency spectrum of the velocity signal is generated by performing a Fast Fourier transform on the velocity signal, and a maximum peak value of the first frequency spectrum, a first bin below the maximum peak value, and a second bin above the maximum peak value are identified.

Abstract: A method of resampling a digital signal involves serially receiving a plurality of samples of said digital signal and applying a plurality of filter coefficients to a first subset of the plurality of samples to generate a first plurality of intermediate results and to a second subset of the samples to generate a second plurality of intermediate results. The first plurality of intermediate results is accumulated to generate a first resampled value, and the second plurality of intermediate results is accumulated to generate a second resampled value. Upon receipt, each signal sample may be used to update each of a plurality of running accumulation values and then discarded before receipt of a next signal sample. Furthermore, multiple signals may be resampled concurrently using a single filter path by multiplexing circuit components, such as memory blocks.

Abstract: A method for acquiring signals received from multiple users in a single burst groups signals by power and sequentially processes the signal groups. A received sum of a plurality of user signals received in a burst is stored, and the transmitted symbols for each signal within a first group of the stored signals is estimated. A modified set of signals is then determined that excludes the signals of the first group. From the modified set of signals, the method continues by canceling multiuser interference among signals within a second group, and estimating transmitted symbols for each signal within the second group. The first and second groups includes all signals within a power band that defines the group, and the first band represents a higher power band than the second. Such iterative processing may continue for sequentially lower power bands until all signals are processed. A receiver is also detailed.

Abstract: A method and apparatus for diminishing display transients and jitter. The method and system disclosed utilizes prior illumination and position histories in displaying and illuminating representations, and elements comprising the representations, on the display. Recognizing repeated representations, finding their prior and current positions, and determining if the difference in position is over a threshold value, diminishes the jitter by displaying the representation in the new position if over the threshold value, or, if it is not over the threshold value, then displaying it in the prior location. The illumination of an element at an intensity, which is based on prior illuminations and/or intensities of the element, diminishes the transients by avoiding flashing or flicker of transient illuminations.

Abstract: A clock signal may be generated for a receiving circuit without requiring an external oscillator. A first digital circuit may convert a first signal edge at an input into a first clock signal at an output, and a second digital circuit, in feedback connection with the first digital circuit, may generate a second signal edge at the input based on the first clock signal at the output. Then, the first circuit may convert the second signal edge at the input to a second clock signal at the output. Thus, the first circuit and the second circuit, in combination, may generate a continuous stream of signal edges at the input and clock signals at the output. The second circuit may communicate with the controller circuit that may indicate that a subsequent clock signal is needed. The controller circuit may send commands and receive status from the receiving circuit.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programming elements (300), each element (300) including a host interface (606) for receiving data and a first control signal from the host circuit (104), a control interface (604) for receiving a second control signal. Each element (300) includes a crosspoint switch (318), and a register array (628) for receiving and storing data from the crosspoint switch (318) according to the first and second control signals, for receiving and storing data from the host interface (606) according to the first and second control signals, and for communicating stored data to the crosspoint switch (318) according to the first and second control signals.

Abstract: A ruggedized mobile computing system for a motor vehicle includes a ruggedized mobile computing device, which can be mounted in the trunk or other convenient location, and a suitable user interface system, such as a display screen, keyboard, etc., mounted in the vehicle cabin. The computing device can accommodate user-removable, plug-in electronic modules that perform specialized processing, communications, control or other specialized tasks relating in some way to the vehicle mission or purpose. The device has a ruggedized enclosure made of a durable material such as sheet metal or high-impact plastic. The enclosure can include a guard that protects cables extending from the front panel from being damaged or inadvertently removed. Cooling and warming systems can be included that maintain the enclosure environment within suitable operating temperatures in hot or cold weather.

Abstract: A circuit 30 for upsampling and upconverting a high rate signal that is divided into M in-phase (I) symbols and M quadrature (Q) symbols. A Nyquist filter 32 upsamples by a factor of k each of the 2M symbols in parallel during one system clock period (CP). The filter 32 has a plurality of 2kM filter components 40, 42, that each provides a continuous output. A plurality of multipliers 50, 52 each upconverts a filter component output with a carrier wave signal 46, 48 that is output from a numerically controlled oscillator 44. A plurality of adders 54 each adds the output of two multipliers 50 to recombine corresponding I and Q samples to output kM samples during a CP. For continuous phase modulation, N parallel bits are input into the filter 32, upsampled in one CP, and accumulated and modulated 82 in parallel in one CP. For analog processing, M (I) and M (Q) symbols are input into an FIR filter 77a, 77b for upsampling, and decimated at a MUX/DAC block 78 for subsequent analog upconversion.

Abstract: A computing device is booted in a manner that enables a software application to begin execution with minimal delay. When the device is powered up, a first processor system begins booting under control of a first operating system, and a second processor system begins booting under control of a second operating system. The first operating system is of a type that generally takes longer to complete booting than the second operating system. As soon as the second processor system has booted up, it begins controlling execution of a software application. Then, when the first processor system has booted up, control over the software application is transferred from the second processor system to the first processor system.