Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programming elements (300), each element (300) including a host interface (606) for receiving data and a first control signal from the host circuit (104), a control interface (604) for receiving a second control signal. Each element (300) includes a crosspoint switch (318), and a register array (628) for receiving and storing data from the crosspoint switch (318) according to the first and second control signals, for receiving and storing data from the host interface (606) according to the first and second control signals, and for communicating stored data to the crosspoint switch (318) according to the first and second control signals.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102). The integrated circuit (102) is in communication with the host circuit (104) and the host circuit (104) is external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programmable elements for data processing (300), each programmable element (300) including a host interface (305) for receiving host data and a host control signal from the host, a crosspoint switch (318), and an interpolation module (310). The host data includes a serial stream of input data values. The interpolation module (310) selectively inserts one or more interpolation data values, such as zero, between selected ones of the input data values according to the host control signal, and communicates the input data values and interpolation data values to the crosspoint switch (318).

Abstract: A geolocation system (10) includes an emitter (12), a plurality of collection nodes (14,16,18), and a control station (20). Each collection node includes a receiver (24) that is operable to receive signals transmitted from the emitter (12), generate a reduced data stream that includes only signal data, and communicate the reduced data stream to the control station (20) along with navigation data. The receiver (24) identifies signal data by detecting an energy level of the raw collection data. More specifically, the receiver (24) determines a bandwidth and a signal-to-noise ratio of each portion of the collection data, and identifies each portion as including signal data if both the bandwidth and the signal-to-noise ratio exceed predetermined threshold amounts. The receiver (24) includes a digital signal processing component (36) for performing calculations used by the receiver (24) to determine the bandwidth and the signal-to-noise ratio.

Abstract: A system for identifying phase transitions in phase-shift keying signals and frequency transitions in frequency-shift keying signals broadly comprises a memory and a computing element capable of: selecting a portion of the signal to analyze, wherein the signal comprises a plurality of data samples; applying a transform to the signal to obtain a frequency spectrum; determining a maximum frequency spectrum corresponding to a carrier frequency; determining a starting approximation value of a slope of the phase transition; calculating a bounded limit of slopes within which to search for the phase transition; selecting a plurality of lines; calculating a sum for the data samples associated with each of the lines; and based on the sum for the data samples, identifying a line that corresponds to a location of the phase transition.

Abstract: A system for identifying phase transitions in phase-shift keying signals and frequency transitions in frequency-shift keying signals broadly comprises a memory and a computing element capable of: selecting a portion of the signal to analyze, wherein the signal comprises a plurality of data samples; applying a transform to the signal to obtain a frequency spectrum; determining a maximum frequency spectrum corresponding to a carrier frequency; determining a starting approximation value of a slope of the phase transition; calculating a bounded limit of slopes within which to search for the phase transition; selecting a plurality of lines, calculating a sum for the data samples associated with each of the lines; and based on the sum for the data samples, identifying a line that corresponds to a location of the phase transition.

Abstract: An architecture for providing data communication between a plurality of field-programmable gate arrays (FPGAS) and a multi-channel data bus comprises a plurality of FPGAs, a switching element, and a multi-channel data bus. Each FPGA includes a multi-channel endpoint component to enable communication with at least a portion of the multi-channel data bus. The switching element couples each FPGA endpoint component with the multi-channel data bus, allowing communication between the FPGA endpoint components and the data bus such that every channel of the data bus is coupled to a channel of an FPGA endpoint component.

Abstract: A method of resampling a digital signal involves serially receiving a plurality of samples of said digital signal and applying a plurality of filter coefficients to a first subset of the plurality of samples to generate a first plurality of intermediate results and to a second subset of the samples to generate a second plurality of intermediate results. The first plurality of intermediate results is accumulated to generate a first resampled value, and the second plurality of intermediate results is accumulated to generate a second resampled value. Upon receipt, each signal sample may be used to update each of a plurality of running accumulation values and then discarded before receipt of a next signal sample. Furthermore, multiple signals may be resampled concurrently using a single filter path by multiplexing circuit components, such as memory blocks.

Abstract: A method of resampling a digital signal involves serially receiving a plurality of samples of said digital signal and applying a plurality of filter coefficients to a first subset of the plurality of samples to generate a first plurality of intermediate results and to a second subset of the samples to generate a second plurality of intermediate results. The first plurality of intermediate results is accumulated to generate a first resampled value, and the second plurality of intermediate results is accumulated to generate a second resampled value. Upon receipt, each signal sample may be used to update each of a plurality of running accumulation values and then discarded before receipt of a next signal sample. Furthermore, multiple signals may be resampled concurrently using a single filter path by multiplexing circuit components, such as memory blocks.

Abstract: A computing architecture comprises a plurality of processing elements to perform data processing calculations, a plurality of memory elements to store the data processing results, and a reconfigurable interconnect network to couple the processing elements to the memory elements. The reconfigurable interconnect network includes a switching element, a control element, a plurality of processor interface units, a plurality of memory interface units, and a plurality of application control units. In various embodiments, the processing elements and the interconnect network may be implemented in a field-programmable gate array.

Abstract: A data coding/decoding system for use with a plurality of users includes an encoder, a transmitter, a receiver, and a decoder. The encoder encodes data to be transmitted over a shared physical transmission medium using an orthogonal or convolution code associated with a receiving user. The transmitter transmits the encoded data. Generally, data may be transmitted simultaneously by a plurality of users. The receiver receives a stream of encoded data and forwards it to the decoder, which decodes it based on the orthogonal or convolution code of the receiving user.

Abstract: Embodiments of the present invention provide a temperature compensating circuit. The circuit generally includes a clock element operable to provide an adjustable clock signal, a buffer element coupled with an analog-to-digital converter and operable to receive the adjustable clock signal, a temperature sensor operable to sense a temperature, and a logic element coupled with the clock element and the temperature sensor. The logic element is operable to acquire the temperature from the temperature sensor and adjust the clock signal based upon the acquired ambient temperature. Such a configuration compensates for temperature variations and reduces system complexity and required component space, thereby providing a compact and efficient design.

Abstract: A method and apparatus for signal tracking utilizing a universal algorithm is disclosed. The method and apparatus generally include acquiring a signal measurement corresponding to a signal, forming a measurement matrix utilizing the acquired signal measurement, and applying the measurement matrix to a recursive filter to determine a geolocation of the signal. Such a configuration enables geolocations to be determined utilizing any signal measurement or combination of signal measurements to eliminate the need to rely on a particular static combination of signal measurements.

Abstract: A cryptographic device may include a programmable hardware component, such as a Field Programmable Gate Array for example, and a processor. The programmable hardware component may encrypt and decrypt data. The programmable hardware component may be securely configured via cryptographically signed and encrypted configuration package. The configuration package may contain a hardware image and executable code. The processor may load the new hardware image onto the programmable hardware device and may execute the executable code to test an operation of the programmable hardware component and the new hardware image. The processor and the programmable hardware component may be physically and/or operationally independent of one another; thus, a security compromise associated with one may not affect the other. Once the programmable hardware component and the hardware image have been tested according to the executable code, the cryptographic device may be ready to encrypt and decrypt user data.

Abstract: In an aspect of the invention, a method is performed in a transceiver for adaptive power amplifier linearization in time division duplex communication systems. The method comprises, in response to a first condition, performing, using a feedback signal generated by receiving subsystem circuitry, adaptive power amplifier linearization on a signal to be transmitted. The method additionally comprises, in response to a second condition, performing operations in order to determine receive data from a received radio frequency (RF) signal. The operations use at least the receiving subsystem circuitry. In a further aspect of the present invention, a transceiver is disclosed.

Abstract: A circuit 30 for upsampling and upconverting a high rate signal that is divided into M in phase (I) symbols and M quadrature (Q) symbols. A Nyquist filter 32 upsamples by a factor of k each of the 2M symbols in parallel during one system clock period (CP). The filter 32 has a plurality of 2kM filter components 40, 42, that each provides a continuous output. A plurality of multipliers 50, 52 each upconverts a filter component output with a carrier wave signal 46, 48 that is output from a numerically controlled oscillator 44. A plurality of adders 54 each adds the output of two multipliers 50 to recombine corresponding I and Q samples to output kM samples during a CP. For continuous phase modulation, N parallel bits are input into the filter 32, upsampled in one CP, and accumulated and modulated 82 in parallel in one CP. For analog processing, M (I) and M (Q) symbols are input into an FIR filter 77a, 77b for upsampling, and decimated at a MUX/DAC block 78 for subsequent analog upconversion.

Abstract: A Personal Computer Memory Card International Association (PCMCIA) card may establish, via a non-secure network, a secure communications channel between a computer and a secure network. The non-secure network may define a first address space. The secure network may define a second address space. The PCMCIA card may include a cryptography module, a network adapter, and/or a processor. The cryptography module may provide Type 1 cryptography of data communicated between the computer and the secure network. The network adapter may be in communication with the non-secure network and may be associated with a first network address from the first address space. The processor may be in communication with the secure network via the cryptography module and the network adapter. The processor may identify a second network address for the computer from the second address space and may communicate the second network address to the computer, for example via dynamic host control protocol (DHCP).

Abstract: A device that includes a first processor, a second processor, and an encryption module in communication with the first processor and the second processor may be used to accept conditions for access to the network. The first processor may receive condition data, and in response, may send an acceptance signal via the encryption module to the second processor. The second processor may receive the acceptance signal and, in response, may send acceptance data to a gatekeeper. The encryption module may block unencrypted data other than the acceptance signal from being communicated from the first processor to the second processor. The encryption module may support type 1 encryption.

Abstract: Methods and apparatus operable to estimate the geolocation of a signal emitter. In some embodiments, the methods comprise acquiring collection data from a plurality of collector elements, computing a plurality of candidate geolocations from the acquired collection data, and applying a clustering analysis to the candidate geolocations to estimate the geolocation of the signal emitter.

Abstract: A solid-state electronic avionics display instrument includes a needle-like display mounted within a housing in a manner that emulates the manner in which prior electro-mechanical needle indicator mechanisms have been mounted in such housings so as to indicate a value along an arcuate scale. New aircraft can be fitted with such instruments initially, while existing aircraft can be retrofitted with such instruments to replace existing electro-mechanical mechanism-based avionics instruments.

Abstract: A Personal Computer Memory Card International Association (PCMCIA) card is disclosed. The PCMCIA card may include a cryptographic module, a communications interface, and a processor. The cryptographic module may perform Type 1 encryption of data received from a computer into which the card is inserted. The cryptographic module may support High Assurance Internet Protocol Encryption (HAIPE). The communications interface may provide connectivity to a network adapter. The communications interface may include a Universal Serial Bus (USB) interface. The processor may detect whether a network adapter is coupled to the communications interface, identify a device driver that corresponds to the network adapter, and employ the device driver to provide operative communication between the cryptographic module and the network adapter. The PCMCIA card may contain a datastore that maintains a plurality device drivers. For example, the plurality of device drivers support any one of IEEE 802.x, Ethernet, V.