Abstract: An apparatus for covertly marking a target includes a housing sized and configured to simulate a portable electronic device; a reservoir positioned in the housing for holding a quantity of miniature markers; and a dispersing mechanism positioned in or on the housing for dispersing the markers onto the target.

Abstract: An integrated circuit in communication with a host circuit includes an interconnect bus and a plurality of programmable elements. Each of the programmable elements includes a control interface for receiving a control signal, the control signal causing the memory element to selectively operate in one of a plurality of modes. In a first mode, the memory element communicates stored data to the output port upon receiving the control signal; in a second mode the memory element communicates stored data to the output port upon detecting valid data at the input port; in a third mode the memory element stores a first data value consisting of at least a portion of a single data word received at the input port; and in a fourth mode the memory element stores a second data value consisting of at least a portion of each of two separate input values received at the input port. Each programmable element may write data to and read data from a memory element of any of the other programmable elements.

Abstract: A system and method for estimating a geolocation of a non-cooperative target using any reasonable target location estimate. Collectors may acquire actual signal measurements including a direction of arrival (DOA), a target range, a time difference of arrival (TDOA), a range rate, a range sum, and/or a frequency difference of arrival (FDOA). A processing device may receive the actual signal measurements and navigational data regarding the collectors. Then, the processing device may calculate an estimated target location as a solution to a nonlinear optimization problem where an objective function to be minimized is a weighted sum-of-squares of differences between the actual signal measurements and calculated values corresponding to signal measurements that theoretically should be produced for a particular target location. The algorithm used to solve this problem may be a globally convergent algorithm, such as a Levenberg-Marquardt algorithm.

Abstract: The present invention is a method and computer program for equalizing group delay and magnitude of a system for which a system response is known. The method and computer program are implemented via a finite impulse response (“FIR”) filter for the system, and the method broadly comprises the steps of: evaluating a desired response for the system as a function of an amplitude of the system and a phase of the system; separating the phase of the system into a linear component and a non-linear component; performing a first optimization by minimizing a weighted error between a desired response for the system and a cascaded response for the system as a function of an equalizing filter and a phase slope so as to obtain at least one local smallest error E(?) as a function of phase slope; and once the local smallest error E(?) is known, performing a second optimization to locate any existing global smallest error, wherein the global smallest error is within a set distance from the local smallest error.

Abstract: A mobile communication device includes a processor; a data acquisition device for acquiring data and providing it to the processor; a transceiver for transmitting at least some of the acquired data to an external device; and a low-power clock. The low-power clock counts down a random delay time period and temporarily shifts the processor and the transceiver from low-power sleep modes to active wake modes so that the processor and transceiver can transmit at least some of the acquired data to the external device while in their active wake modes.

Abstract: A system and method for symbol rate estimation using vector velocity that does not require any prior knowledge of the signal's structure and is accurate in the presence of frequency offset and noise. An input signal is converted to a symbol constellation path signal, and a velocity signal representing a velocity of the symbol constellation path signal is generated. A first frequency spectrum of the velocity signal is generated by performing a Fast Fourier transform on the velocity signal, and a maximum peak value of the first frequency spectrum, a first bin below the maximum peak value, and a second bin above the maximum peak value are identified.

Abstract: A method of resampling a digital signal involves serially receiving a plurality of samples of said digital signal and applying a plurality of filter coefficients to a first subset of the plurality of samples to generate a first plurality of intermediate results and to a second subset of the samples to generate a second plurality of intermediate results. The first plurality of intermediate results is accumulated to generate a first resampled value, and the second plurality of intermediate results is accumulated to generate a second resampled value. Upon receipt, each signal sample may be used to update each of a plurality of running accumulation values and then discarded before receipt of a next signal sample. Furthermore, multiple signals may be resampled concurrently using a single filter path by multiplexing circuit components, such as memory blocks.

Abstract: A system for identifying a person includes at least one biometric sensor for sensing a biometric characteristic of the person; at least one signal sensor for sensing a signal emitted from a device carried by the person; and a computing device for comparing the sensed biometric characteristic and the sensed signal to known characteristics of the person in an attempt to identify the person.

Abstract: An environmentally sealed electronic device with an internal activation circuit that does not require a constant interrogation signal to maintain power to its internal circuitry. The electronic device includes sensor circuitry for gathering or sensing data; an internal battery for powering the sensor circuitry; and an internal activation circuit for activating the sensor circuitry. The sensor circuitry may include a temperature sensor, a location sensor, a signal sensor, a sound detector, a motion sensor, or any other device that senses or gathers data. The battery may be any type of energy storage device such as a lithium or alkaline battery. The activation circuit includes a receiver for receiving a radio frequency signal from an external source and a switch for connecting the battery to the sensor circuitry in response to the receiver. The switch is operable to maintain connection of the battery to the sensor circuitry after the radio frequency signal ceases.

Abstract: A system for solving large-scale matrix equations comprises a plurality of field programmable gate arrays (FPGAs), a plurality of memory elements, a plurality of memory element controllers, and a plurality of processing elements. The FPGAs may include a plurality of configurable logic elements and a plurality of configurable storage elements. The memory elements may be accessible by the FPGAs and may store a matrix and a first vector. The memory element controllers may be formed from configurable logic elements and configurable storage elements and may supply at least a portion of a row of the matrix and at least a portion of the first vector. Each processing element may receive at least the row of the matrix and the first vector and solve an iteration for one element of the first vector.

Abstract: A system for determining the median of a plurality of data values comprises a plurality of field programmable gate arrays (FPGA), a plurality of inter FPGA links, an input router, a plurality of median modules, and a plurality of output transfer modules. Each FPGA includes a plurality of configurable logic elements and configurable storage elements from which the other components are formed. The inter FPGA link allows communication from one FPGA to another. The input router receives the plurality of data values and creates a plurality of data streams. The median module receives at least one data stream, increments a plurality of counters corresponding to a single data value within the range of data values, and determines the median by accumulating the contents of each counter. The output transfer module transfers the median to an external destination along with performance statistics of the determination of the median.

Abstract: Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Dynamically-sized data packets, sized in accordance with the amount of data ready to be sent, are transferred between the devices and/or interfaces on the card.

Abstract: A system for correcting image characteristic data from a plurality of pixels comprises at least one field programmable gate array (FPGA), a lookup table, and a correction module. The FPGA may include a plurality of configurable logic elements and a plurality of configurable storage elements. The lookup table may be accessible by the FPGA and may store a plurality of correction components associated with each pixel, including a gain value, an offset value, and a bad pixel value. The correction module may be formed from the configurable logic elements and configurable storage elements and may receive the characteristic data and the correction components. The correction module may generate corrected data for each characteristic data by utilizing the gain value, the offset value, and the bad pixel value.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programming elements (300), each element (300) including a host interface (606) for receiving data and a first control signal from the host circuit (104), a control interface (604) for receiving a second control signal. Each element (300) includes a crosspoint switch (318), and a register array (628) for receiving and storing data from the crosspoint switch (318) according to the first and second control signals, for receiving and storing data from the host interface (606) according to the first and second control signals, and for communicating stored data to the crosspoint switch (318) according to the first and second control signals.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programming elements (300), each element (300) including a host interface (606) for receiving data and a first control signal from the host circuit (104), a control interface (604) for receiving a second control signal. Each element (300) includes a crosspoint switch (318), and a register array (628) for receiving and storing data from the crosspoint switch (318) according to the first and second control signals, for receiving and storing data from the host interface (606) according to the first and second control signals, and for communicating stored data to the crosspoint switch (318) according to the first and second control signals.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102). The integrated circuit (102) is in communication with the host circuit (104) and the host circuit (104) is external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programmable elements for data processing (300), each programmable element (300) including a host interface (305) for receiving host data and a host control signal from the host, a crosspoint switch (318), and an interpolation module (310). The host data includes a serial stream of input data values. The interpolation module (310) selectively inserts one or more interpolation data values, such as zero, between selected ones of the input data values according to the host control signal, and communicates the input data values and interpolation data values to the crosspoint switch (318).

Abstract: A geolocation system (10) includes an emitter (12), a plurality of collection nodes (14,16,18), and a control station (20). Each collection node includes a receiver (24) that is operable to receive signals transmitted from the emitter (12), generate a reduced data stream that includes only signal data, and communicate the reduced data stream to the control station (20) along with navigation data. The receiver (24) identifies signal data by detecting an energy level of the raw collection data. More specifically, the receiver (24) determines a bandwidth and a signal-to-noise ratio of each portion of the collection data, and identifies each portion as including signal data if both the bandwidth and the signal-to-noise ratio exceed predetermined threshold amounts. The receiver (24) includes a digital signal processing component (36) for performing calculations used by the receiver (24) to determine the bandwidth and the signal-to-noise ratio.

Abstract: A system for identifying phase transitions in phase-shift keying signals and frequency transitions in frequency-shift keying signals broadly comprises a memory and a computing element capable of: selecting a portion of the signal to analyze, wherein the signal comprises a plurality of data samples; applying a transform to the signal to obtain a frequency spectrum; determining a maximum frequency spectrum corresponding to a carrier frequency; determining a starting approximation value of a slope of the phase transition; calculating a bounded limit of slopes within which to search for the phase transition; selecting a plurality of lines; calculating a sum for the data samples associated with each of the lines; and based on the sum for the data samples, identifying a line that corresponds to a location of the phase transition.

Abstract: A system for identifying phase transitions in phase-shift keying signals and frequency transitions in frequency-shift keying signals broadly comprises a memory and a computing element capable of: selecting a portion of the signal to analyze, wherein the signal comprises a plurality of data samples; applying a transform to the signal to obtain a frequency spectrum; determining a maximum frequency spectrum corresponding to a carrier frequency; determining a starting approximation value of a slope of the phase transition; calculating a bounded limit of slopes within which to search for the phase transition; selecting a plurality of lines, calculating a sum for the data samples associated with each of the lines; and based on the sum for the data samples, identifying a line that corresponds to a location of the phase transition.

Abstract: An architecture for providing data communication between a plurality of field-programmable gate arrays (FPGAS) and a multi-channel data bus comprises a plurality of FPGAs, a switching element, and a multi-channel data bus. Each FPGA includes a multi-channel endpoint component to enable communication with at least a portion of the multi-channel data bus. The switching element couples each FPGA endpoint component with the multi-channel data bus, allowing communication between the FPGA endpoint components and the data bus such that every channel of the data bus is coupled to a channel of an FPGA endpoint component.