Abstract: A method of resampling a digital signal involves serially receiving a plurality of samples of said digital signal and applying a plurality of filter coefficients to a first subset of the plurality of samples to generate a first plurality of intermediate results and to a second subset of the samples to generate a second plurality of intermediate results. The first plurality of intermediate results is accumulated to generate a first resampled value, and the second plurality of intermediate results is accumulated to generate a second resampled value. Upon receipt, each signal sample may be used to update each of a plurality of running accumulation values and then discarded before receipt of a next signal sample. Furthermore, multiple signals may be resampled concurrently using a single filter path by multiplexing circuit components, such as memory blocks.

Abstract: A method of resampling a digital signal involves serially receiving a plurality of samples of said digital signal and applying a plurality of filter coefficients to a first subset of the plurality of samples to generate a first plurality of intermediate results and to a second subset of the samples to generate a second plurality of intermediate results. The first plurality of intermediate results is accumulated to generate a first resampled value, and the second plurality of intermediate results is accumulated to generate a second resampled value. Upon receipt, each signal sample may be used to update each of a plurality of running accumulation values and then discarded before receipt of a next signal sample. Furthermore, multiple signals may be resampled concurrently using a single filter path by multiplexing circuit components, such as memory blocks.

Abstract: A data coding/decoding system for use with a plurality of users includes an encoder, a transmitter, a receiver, and a decoder. The encoder encodes data to be transmitted over a shared physical transmission medium using an orthogonal or convolution code associated with a receiving user. The transmitter transmits the encoded data. Generally, data may be transmitted simultaneously by a plurality of users. The receiver receives a stream of encoded data and forwards it to the decoder, which decodes it based on the orthogonal or convolution code of the receiving user.

Abstract: A computing architecture comprises a plurality of processing elements to perform data processing calculations, a plurality of memory elements to store the data processing results, and a reconfigurable interconnect network to couple the processing elements to the memory elements. The reconfigurable interconnect network includes a switching element, a control element, a plurality of processor interface units, a plurality of memory interface units, and a plurality of application control units. In various embodiments, the processing elements and the interconnect network may be implemented in a field-programmable gate array.

Abstract: Embodiments of the present invention provide a temperature compensating circuit. The circuit generally includes a clock element operable to provide an adjustable clock signal, a buffer element coupled with an analog-to-digital converter and operable to receive the adjustable clock signal, a temperature sensor operable to sense a temperature, and a logic element coupled with the clock element and the temperature sensor. The logic element is operable to acquire the temperature from the temperature sensor and adjust the clock signal based upon the acquired ambient temperature. Such a configuration compensates for temperature variations and reduces system complexity and required component space, thereby providing a compact and efficient design.

Abstract: A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate a first product, and a first linear solver module for calculating an updated first element of the vector variable using the first product. A second circuit includes a second multiplication module for multiplying a second row of the matrix by a second instance of the vector variable to generate a second product, and a second linear solver module for calculating an updated second element of the vector variable using the second product. An interface module updates the second instance of the vector variable with the first updated element, and updates the first instance of the vector variable with the second updated element.

Abstract: An automatic background noise estimator (BNE) seed calculator for determining a starting point for a BNE circuit which tracks the noise floor received by a receiver. The BNE seed calculator may sample a plurality of data points from the receiver and calculate the magnitude of each point. The seed calculator may then determine the peak magnitude value, a plurality of mean values, and the variance of the sampled points. A plurality of lookup tables are used to compare the peak, mean, and variance values with simulated peak, mean, and variance values to estimate the noise floor level of the actual signal and use that to determine the optimum BNE seed value. Simulation software such as MATLAB is used to develop the lookup tables by simulating peak, mean, and variance values based on a plurality of signal-to-noise ratios (SNR).

Abstract: A method of resampling a digital signal involves serially receiving a plurality of samples of said digital signal and applying a plurality of filter coefficients to a first subset of the plurality of samples to generate a first plurality of intermediate results and to a second subset of the samples to generate a second plurality of intermediate results. The first plurality of intermediate results is accumulated to generate a first resampled value, and the second plurality of intermediate results is accumulated to generate a second resampled value. Upon receipt, each signal sample may be used to update each of a plurality of running accumulation values and then discarded before receipt of a next signal sample. Furthermore, multiple signals may be resampled concurrently using a single filter path by multiplexing circuit components, such as memory blocks.

Abstract: A method and apparatus for signal tracking utilizing a universal algorithm is disclosed. The method and apparatus generally include acquiring a signal measurement corresponding to a signal, forming a measurement matrix utilizing the acquired signal measurement, and applying the measurement matrix to a recursive filter to determine a geolocation of the signal. Such a configuration enables geolocations to be determined utilizing any signal measurement or combination of signal measurements to eliminate the need to rely on a particular static combination of signal measurements.

Abstract: Methods and apparatus operable to estimate the geolocation of a signal emitter. In some embodiments, the methods comprise acquiring collection data from a plurality of collector elements, computing a plurality of candidate geolocations from the acquired collection data, and applying a clustering analysis to the candidate geolocations to estimate the geolocation of the signal emitter.

Abstract: A computing system (10) includes a plurality of hardware computing resources (12-36) controlled at least in part by a plurality of autonomous computing agents (40,42,44). Each autonomous computing agent (40,42,44) includes or has access to operating information including processing information (46), resource information (48), optimization information (50), and communication information (52). The computing agents (40,42,44) collaborate to optimize performance of the system (10) and to assign computing tasks to the resources (12-36) according to a predetermined strategy. The predetermined strategy may seek to optimize speed, power, or communication efficiency of the system 10. Each agent (40,42,44) may optimize performance of the system (10) by assigning tasks to best-fit resources or by reconfiguring one or more resources.

Abstract: A programmable accumulation module (324) with an embedded register array comprises a crosspoint switch (318), a control interface for receiving a control signal (359), a register array circuit (352), a multiplier module (348) for receiving two input values from the crosspoint switch (318) and multiplying the values, and an adder module (350) for adding an output of the multiplier module (348) with an output of the register array circuit (352). The register array circuit includes a plurality of data registers (356), an input multiplexer (354) for receiving an add result from the adder module and communicating the add result to one of the plurality of data registers (356) according to the control signal, and an output multiplexer (358) for receiving an output value from each of the plurality of data registers (356) and selectively communicating one of the plurality of output values to the adder module (350) according to the control signal.

Abstract: An integrated circuit (102) in communication with a host circuit (104) includes an interconnect bus (344) and a plurality of programmable elements (116-130). Each of the programmable elements (116-130) includes a control interface (354) for receiving a control signal, the control signal causing the memory element (338) to selectively operate in one of a plurality of modes. In a first mode, the memory element (338) communicates stored data to the output port upon receiving the control signal; in a second mode the memory element (338) communicates stored data to the output port upon detecting valid data at the input port; in a third mode the memory element stores a first data value consisting of at least a portion of a single data word received at the input port; and in a fourth mode the memory element (338) stores a second data value consisting of at least a portion of each of two separate input values received at the input port.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102). The integrated circuit (102) is in communication with the host circuit (104) and the host circuit (104) is external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programmable elements for data processing (300), each programmable element (300) including a host interface (305) for receiving host data and a host control signal from the host, a crosspoint switch (318), and an interpolation module (310). The host data includes a serial stream of input data values. The interpolation module (310) selectively inserts one or more interpolation data values, such as zero, between selected ones of the input data values according to the host control signal, and communicates the input data values and interpolation data values to the crosspoint switch (318).

Abstract: Methods and apparatus operable to estimate the geolocation of a signal emitter. In some embodiments, the methods comprise acquiring collection data from a plurality of collector elements, computing a plurality of candidate geolocations from the acquired collection data, and applying a clustering analysis to the candidate geolocations to estimate the geolocation of the signal emitter.

Abstract: A method and apparatus for correcting a phase of a phase-modulated signal for blind demodulation. The method and apparatus generally include the creation of a plurality of angle bins, wherein each constellation point of the phase-modulated signal is assigned to an angle bin, depending on its phase angle. A histogram is formed of the angle bins and cross correlated with a template signal model histogram. The maximum value of the cross correlation determines a correction angle by which the phase angle of all the phase-modulated constellation points is multiplied.

Abstract: A circuit (26) performs a discrete Walsh transform using a reduced set of arithmetic operators. The circuit (26) comprises a first memory component (32), an adder (36), a subtractor (38), a second memory component (40), and a controller (52). In each of a plurality of stages, the controller (52) enables the first memory component (32) to communicate each of a plurality of pairs of values stored therein to the adder (36) and to the subtractor (38). The controller (52) enables the second memory component (40) to store each of a plurality of results from the adder (36) and the subtractor (38) and to communicate the stored results to the first memory component (32) for use in a subsequent stage.

Abstract: A system and method for symbol rate estimation using vector velocity that does not require any prior knowledge of the signal's structure and is accurate in the presence of frequency offset and noise. An input signal is converted to a symbol constellation path signal, and a velocity signal representing a velocity of the symbol constellation path signal is generated. A first frequency spectrum of the velocity signal is generated by performing a Fast Fourier transform on the velocity signal, and a maximum peak value of the first frequency spectrum, a first bin below the maximum peak value, and a second bin above the maximum peak value are identified.

Abstract: Embodiments of the present invention provide a method and apparatus for compressed sensing. In some embodiments, the apparatus (10) generally includes a receiving element (12) operable to receive an input signal, an integrate/dump circuit (14), a sampling element (16), and a processor (18). The integrate/dump circuit (14) is operable to integrate at least a portion of the received signal to provide an integrated signal and the sampling element (16) is operable to sample the integrated signal at a first sampling rate which is less than the Nyquist rate for the input signal. The processor (18) is operable to form a compressed sensing matrix utilizing a first set of time indices corresponding to the first sampling rate, form a measurement vector utilizing at least a portion of the sampled signal, and reconstruct at least a portion of the input signal utilizing the compressed sensing matrix and the measurement vector.

Abstract: A geolocation system (10) includes an emitter (12), a plurality of collection nodes (14,16,18), and a control station (20). Each collection node includes a receiver (24) that is operable to receive signals transmitted from the emitter (12), generate a reduced data stream that includes only signal data, and communicate the reduced data stream to the control station (20) along with navigation data. The receiver (24) identifies signal data by detecting an energy level of the raw collection data. More specifically, the receiver (24) determines a bandwidth and a signal-to-noise ratio of each portion of the collection data, and identifies each portion as including signal data if both the bandwidth and the signal-to-noise ratio exceed predetermined threshold amounts. The receiver (24) includes a digital signal processing component (36) for performing calculations used by the receiver (24) to determine the bandwidth and the signal-to-noise ratio.