Patents Assigned to Lam Research Corporation
  • Patent number: 10727143
    Abstract: A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 28, 2020
    Assignee: Lam Research Corporation
    Inventors: Pulkit Agarwal, Adrien Lavoie, Ravi Kumar, Purushottam Kumar
  • Patent number: 10725485
    Abstract: A temperature controller for a substrate support in a substrate processing system includes a power parameter module configured to calculate a power parameter indicative of power supplied to the substrate support. A coolant temperature parameter module configured to calculate a coolant temperature parameter indicative of a temperature of a coolant supplied to the substrate support. A heat transfer gas parameter module is configured to calculate a heat transfer gas parameter indicative of flow rates of a heat transfer gas supplied to the substrate support. A temperature calculation module is configured to calculate a temperature of the substrate support using the power parameter, the coolant temperature parameter, and the heat transfer gas parameter.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 28, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: David Joseph Wetzel, Alexander Bleakie, Jacob Frederick Theisen
  • Patent number: 10727046
    Abstract: A method for performing gap fill of a feature on a substrate includes the following operations: (a) moving the substrate into a process chamber; (b) performing a plurality of cycles of an ALD process; (c) purging process gases from the ALD process from the process chamber; (d) performing a plasma treatment on the substrate by introducing a fluorine-containing gas into the process chamber and applying RF power to the fluorine-containing gas to generate a fluorine plasma in the process chamber; (e) purging process gases from the plasma treatment from the process chamber; (f) repeating operations (b) through (e) until a predefined number of cycles has been performed.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 28, 2020
    Assignee: Lam Research Corporation
    Inventors: Joseph Abel, Adrien Lavoie, Purushottam Kumar
  • Patent number: 10727073
    Abstract: Methods and apparatuses for etching semiconductor material on substrates using atomic layer etching by chemisorption, by deposition, or by both chemisorption and deposition mechanisms in combination with oxide passivation are described herein. Methods involving atomic layer etching using a chemisorption mechanism involve exposing the semiconductor material to chlorine to chemisorb chlorine onto the substrate surface and exposing the modified surface to argon to remove the modified surface. Methods involving atomic layer etching using a deposition mechanism involve exposing the semiconductor material to a sulfur-containing gas and hydrogen to deposit and thereby modify the substrate surface and removing the modified surface.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: July 28, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Samantha Tan, Wenbing Yang, Keren Jacobs Kanarik, Thorsten Lill, Yang Pan
  • Patent number: 10727089
    Abstract: A method for selectively etching one exposed material of a substrate relative to another exposed material of the substrate includes a) arranging the substrate in a processing chamber; b) setting a chamber pressure; c) setting an RF frequency and an RF power for RF plasma; d) supplying a plasma gas mixture to the processing chamber; e) striking the RF plasma in the processing chamber in one of an electric mode (E-mode) and a magnetic mode (H-mode); and f) during plasma processing of the substrate, changing at least one of the chamber pressure, the RF frequency, the RF power and the plasma gas mixture to switch from the one of the E-mode and the H-mode to the other of the E-mode and the H-mode.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: July 28, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: James Eugene Caron, Ivelin Angelov, Joon Hong Park, Dengliang Yang
  • Patent number: 10720346
    Abstract: A substrate support in a semiconductor plasma processing apparatus, comprises multiple independently controllable thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the thermal zones. A substrate support in which the substrate support is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the substrate support include bonding together ceramic or polymer sheets having thermal zones, power supply lines, power return lines and vias.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: July 21, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Harmeet Singh, Keith Gaff, Neil Benjamin, Keith Comendant
  • Patent number: 10720314
    Abstract: An apparatus for confining plasma within a plasma processing chamber is provided. The plasma processing chamber includes a lower electrode for supporting a substrate and an upper electrode disposed over the lower electrode. The apparatus is a confinement ring that includes a lower horizontal section extending between an inner lower radius and an outer radius of the confinement ring. The lower horizontal section includes an extension section that bends vertically downward at the inner lower radius, and the lower horizontal section further includes a plurality of slots. The confinement ring further includes an upper horizontal section extending between an inner upper radius and the outer radius of the confinement ring and a vertical section that integrally connects the lower horizontal section with the upper horizontal section. The extension section of the lower horizontal section is configured to surround the lower electrode when installed in the plasma processing chamber.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 21, 2020
    Assignee: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Akira Koshiishi, Alexei Marakhatanov
  • Patent number: 10714354
    Abstract: Methods of and apparatuses for laterally etching semiconductor substrates using an atomic layer etch process involving exposing an oxidized surface of a semiconductor substrate to a fluorine-containing etch gas and heating the substrate to remove non-volatile etch byproducts by a sublimation mechanism are provided herein. Methods also including additionally pulsing a hydrogen-containing gas when pulsing the fluorine-containing etch gas. Apparatuses also include an ammonia mixing manifold suitable for separately preparing and mixing ammonia for use in various tools.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: July 14, 2020
    Assignee: Lam Research Corporation
    Inventors: Tom Kamp, Neema Rastgar, Michael Carl Drymon
  • Patent number: 10714436
    Abstract: Systems and methods for achieving uniformity across a redistribution layer are described. One of the methods includes patterning a photoresist layer over a substrate. The patterning defines a region for a conductive line and a via disposed below the region for the conductive line. The method further includes depositing a conductive material in between the patterned photoresist layer, such that the conductive material fills the via and the region for the conductive line. The depositing causes an overgrowth of conductive material of the conductive line to form a bump of the conductive material over the via. The method also includes planarizing a top surface of the conductive line while maintaining the patterned photoresist layer present over the substrate. The planarizing is facilitated by exerting a horizontal shear force over the conductive line and the bump. The planarizing is performed to flatten the bump.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: July 14, 2020
    Assignee: Lam Research Corporation
    Inventors: Bryan L. Buckalew, Thomas A. Ponnuswamy, Steven T. Mayer, Stephen J. Banik, II, Justin Oberst
  • Patent number: 10715095
    Abstract: A radiofrequency (RF) filter includes an inductive element having multiple coil sections collectively forming an undivided coil of a cable of twisted magnetic wires. At least two adjacent coil sections have different turn pitches. The cable of twisted magnetic wires includes two wires per channel and is configured for at least one channel. The cable of twisted magnetic wires at a first end of the inductive element is configured for connection to an electrical component that is to receive power from a power supply. The cable of twisted magnetic wires at a second end of the inductive element is configured for connection to the power supply. Terminating capacitive elements are electrically connected between a reference ground potential and a respective wire of the cable of twisted magnetic wires at respective locations between the second end of the inductive element and the power supply.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: July 14, 2020
    Assignee: Lam Research Corporation
    Inventors: Maolin Long, Alex Paterson
  • Patent number: 10711366
    Abstract: In one example, an electroplating system comprising a bath reservoir having a first inlet for feeding fresh electrolyte solution into the bath reservoir and a first outlet for bleeding used electrolyte solution out of the bath reservoir, a second inlet for receiving recycled electrolyte solution into the bath reservoir, and a second outlet for discharge of electrolyte solution from the bath reservoir. A plating cell is providing for electroplating an object, the plating cell has an inlet in direct or indirect fluid communication with the bath reservoir, and an outlet for discharge of electrolyte solution from the plating cell. An extraction column extracts by-products generated by the plating cell and has an inlet in direct or indirect fluid communication with the outlet of the plating cell, and an outlet for discharge of electrolyte solution from the extraction column.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: July 14, 2020
    Assignee: Lam Research Corporation
    Inventors: Tighe A. Spurlin, Jonathan D. Reid
  • Patent number: 10711364
    Abstract: Apparatuses and methods are provided for depositing a metal layer on a wafer. A secondary weir is positioned at a region below the primary weir such that overflowed plating solution over the primary weir during electroplating flows in a substantially azimuthally uniform manner. Methods are provided for electroplating wafers by increasing flow rate between wafer processes while plating solution flows over a primary weir, remains in contact with the overflowing plating solution, and flows onto the secondary weir such that overflow is substantially azimuthally uniform.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 14, 2020
    Assignee: Lam Research Corporation
    Inventors: Daniel Mark Dinneen, Jingbin Feng
  • Patent number: 10714345
    Abstract: A method for forming a junction in a germanium (Ge) layer of a substrate includes arranging the substrate in a processing chamber. The method includes performing a plasma pretreatment on the substrate in the processing chamber for a predetermined pretreatment period using a pretreatment plasma gas mixture including hydrogen gas species. The method includes supplying a doping plasma gas mixture to the processing chamber including a phosphorous (P) gas species and an antimony (Sb) gas species. The method includes striking plasma in the processing chamber for a predetermined doping period. The method includes annealing the substrate during a predetermined annealing period to form the junction in the germanium (Ge) layer.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: July 14, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Yunsang Kim, Hyuk-Jun Kwon
  • Publication number: 20200219725
    Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.
    Type: Application
    Filed: March 20, 2020
    Publication date: July 9, 2020
    Applicant: Lam Research Corporation
    Inventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick van Cleemput, Bart J. van Schravendijk
  • Publication number: 20200219758
    Abstract: Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO2 and SiN can be selectively etched using a plasma formed in an Hz-containing process gas. The etching creates a recessed feature in place of the tin oxide between the surrounding materials. A third material, such as SiO2 is deposited over the resulting recessed feature without fully filling the recessed feature, forming an air gap. A method for selectively etching tin oxide in a presence of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, or SiCN, includes, in some embodiments, contacting the substrate with a plasma formed in a process gas comprising at least about 50% Hz. Etching of tin oxide can be performed without using an external bias at the substrate and is preferably performed at a temperature of less than about 100° C.
    Type: Application
    Filed: March 20, 2020
    Publication date: July 9, 2020
    Applicant: Lam Research Corporation
    Inventors: Patrick van Cleemput, Seshasayee Varadarajan, Bart J. van Schravendijk
  • Patent number: 10704149
    Abstract: A method for processing a substrate in a substrate processing system includes selectively delivering at least one of a precursor, a deposition carrier gas, and a post deposition purge gas to a processing chamber. The method includes depositing film on the substrate by generating radio frequency (RF) plasma in the processing chamber between an upper electrode and a lower electrode while supplying an RF voltage to one of the upper electrode and the lower electrode and while the precursor and the deposition carrier gas is delivered. The method includes selectively supplying a direct current (DC) bias voltage to the upper electrode or the lower electrode; moving the substrate relative to a pedestal supporting the substrate while generating the DC bias voltage; and delivering the post deposition purge gas while supplying at least a portion of the DC bias voltage to the upper electrode or the lower electrode.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: July 7, 2020
    Assignee: Lam Research Corporation
    Inventors: Arul Dhas, Kareem Boumatar, Christopher Ramsayer
  • Patent number: 10707113
    Abstract: An end effector includes a body, a first tine, and a second tine. The body includes first, second, and third substrate support pads, the first substrate support pad defines a first height, the second substrate support pad defines a second height less than the first height, and the third substrate support pad defines a third height equal to the first height. The first tine includes fourth and fifth substrate support pads, the fourth substrate support pad defines a fourth height equal to the second height, and the fifth substrate support pad defines a fifth height equal to the first and third heights. The second tine includes sixth and seventh substrate support pads, the sixth substrate support pad defines a sixth height equal to the first, third, and fifth heights, the seventh substrate support pad defines a seventh height equal to the second and fourth heights.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 7, 2020
    Assignee: Lam Research Corporation
    Inventors: Ross Embertson, Brandon Senn, Austin Ngo, Matthew J. Rodnick
  • Patent number: 10707110
    Abstract: A substrate support for supporting a substrate in a substrate processing system includes a plurality of thermal elements. The thermal elements are arranged in one or more thermal zones, and each of the thermal zones includes at least one of the thermal elements. Each of the thermal elements includes a first resistive material having a positive thermal coefficient of resistance and a second resistive material having a negative thermal coefficient of resistance. The second resistive material is electrically connected to the first resistive material. At least one of the first resistive material and the second resistive material of each of the thermal elements is electrically connected to a power supply to receive power, and each of the thermal elements heats a respective one of the thermal zones based on the received power. At least one ceramic layer is arranged adjacent to the thermal elements.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 7, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventor: Eric A. Pape
  • Patent number: 10707056
    Abstract: Systems and methods for determining ion energy are described. One of the methods includes detecting output of a generator to identify a generator output complex voltage and current (V&I). The generator is coupled to an impedance matching circuit and the impedance matching circuit is coupled to an electrostatic chuck (ESC). The method further includes determining from the generator output complex V&I a projected complex V&I at a point along a path between an output of a model of the impedance matching circuit and a model of the ESC. The operation of determining of the projected complex V&I is performed using a model for at least part of the path. The method includes applying the projected complex V&I as an input to a function to map the projected complex V&I to a wafer bias value at the ESC model and determining an ion energy from the wafer bias value.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: July 7, 2020
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Bradford J. Lyndaker
  • Patent number: 10697874
    Abstract: A consumable part having a body with a surface is configured to be exposed to plasma during processing in a chamber. The consumable part includes a trigger feature disposed in the body. The trigger feature includes a void, and the void is an identifiable feature on the surface of the body to identify a wear level of the consumable part. The wear level is correlated to a lifetime remaining for the consumable part.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 30, 2020
    Assignee: Lam Research Corporation
    Inventor: Richard Alan Gottscho