Abstract: Embodiments for processing a substrate in a pulsed plasma chamber are provided. A processing apparatus with two chambers, separated by a plate fluidly connecting the chambers, includes a continuous wave (CW) controller, a pulse controller, and a system controller. The CW controller sets the voltage and the frequency for a first radio frequency (RF) power source coupled to a top electrode. The pulse controller is operable to set voltage, frequency, ON-period duration, and OFF-period duration for a pulsed RF signal generated by a second RF power source coupled to the bottom electrode. The system controller is operable to regulate the flow of species between the chambers to assist in the negative-ion etching, to neutralize excessive positive charge on the wafer surface during afterglow in the OFF-period, and to assist in the re-striking of the bottom plasma during the ON-period.

Abstract: Methods for depositing ultrathin films by atomic layer deposition with reduced wafer-to-wafer variation are provided. Methods involve exposing the substrate to soak gases including one or more gases used during a plasma exposure operation of an atomic layer deposition cycle prior to the first atomic layer deposition cycle to heat the substrate to the deposition temperature.

Abstract: Various embodiments herein relate to methods, apparatus, and systems for etching a feature in a substrate. Typically the feature is etched in a dielectric-containing stack. The etching process involves cyclically etching the feature and depositing a protective film on sidewalls of the partially etched feature. These stages are repeated until the feature reaches its final depth. The protective film may have a particular composition, for example including at least one of a tungsten carbonitride, a tungsten sulfide, tin, a tin-containing compound, molybdenum, a molybdenum-containing compound, a ruthenium carbonitride, a ruthenium sulfide, an aluminum carbonitride, an aluminum sulfide, zirconium, and a zirconium-containing compound. A number of optional steps may be taken including, for example, doping the mask layer, pre-treating the substrate prior to deposition, removing the protective film from the sidewalls, and oxidizing any remaining protective film.

Abstract: A carrier plate for receiving a wafer includes a pocket defined in a middle section on a top surface of the carrier plate and has a surface diameter. The pocket defines a substrate support region. A retaining feature of the carrier plate is defined at an outer edge of the pocket. A tapered portion of the carrier plate extends from the retaining feature to an outer diameter. The tapered portion is configured to receive a focus ring. A bottom surface of the carrier plate is configured to sit over a pedestal that is used in a process chamber. A plurality of wafer supports is disposed on a top surface of the substrate support region to support the wafer, when received.

Abstract: A fluid delivery system includes N first valves. Inlets of the N first valves are fluidly connected to N gas sources, respectively, where N is an integer greater than zero. N mass flow controllers include a microelectromechanical (MEMS) Coriolis flow sensor having an inlet in fluid communication with an outlet of a corresponding one of the N first valves. A second valve has an inlet in fluid communication with an outlet of the MEMS Coriolis flow sensor and an outlet supplying fluid to treat a substrate arranged in a processing chamber. A controller in communication with the MEMS Coriolis flow sensor is configured to determine at least one of a mass flow rate and a density of fluid flowing through the MEMS Coriolis flow sensor.

Abstract: A gas delivery system includes a 2-port valve including a first valve located between a first port and a second port. A 4-port valve includes a first node connected to a first port and a second port. A bypass path is located between the third port and the fourth port. A second node is located along the bypass path. A second valve is located between the first node and the second node. A manifold block defines gas flow channels configured to connect the first port of the 4-port valve to a first inlet, configured to connect the second port of the 4-port valve to the first port of the 2-port valve, the third port of the 4-port valve to a second inlet, the second port of the 2-port valve to a first outlet, and the fourth port of the 4-port valve to a second outlet.

Abstract: An electrostatic chuck for a substrate processing system is provided and includes a baseplate, an intermediate layer disposed on the baseplate, and a top plate. The top plate is bonded to the baseplate via the intermediate layer and is configured to electrostatically clamp to a substrate. The top plate includes a monopolar clamping electrode and seals. The monopolar clamping electrode includes a groove opening pattern with coolant gas groove opening sets. The seals separate coolant gas zones. The coolant gas zones include four or more coolant gas zones. Each of the coolant gas zones includes distinct coolant gas groove sets. The top plate includes the distinct coolant gas groove sets. Each of the distinct coolant gas groove sets has one or more coolant gas supply holes and corresponds to a respective one of the coolant gas groove opening sets.

Abstract: An apparatus for electroplating a semiconductor wafer includes an insert member configured to circumscribe a processing region. The insert member has a top surface. A portion of the top surface of the insert member has an upward slope that slopes upward from a peripheral area of the top surface of the insert member toward the processing region. The apparatus also includes a seal member having an annular-disk shape. The seal member is positioned on the top surface of the insert member. The seal member is flexible such that an outer radial portion of the seal member conforms to the upward slope of the top surface of the insert member and such that an inner radial portion of the seal member projects inward toward the processing region.

Abstract: The invention relates to a device for pulsed laser deposition and a substrate with a substrate surface, which device includes: a substrate holder for holding the substrate; a target arranged facing the substrate surface of the substrate; a velocity filter arranged between the substrate and the target; a pulsed laser directed onto the target at a target spot for generating a plasma plume of target material; and a plasma hole plate arranged between the target and the substrate. The plasma hole plate has a plasma passage opening divided in an upstream section and a downstream section by a dividing plane. The target spot coincides with the dividing plane, and the surface area of the upstream section is larger than the surface area of the downstream section.

Abstract: A method for forming features over a wafer with a carbon based deposition is provided. The carbon based deposition is pretuned, wherein the pretuning causes a non-uniform removal of some of the carbon based deposition. An oxide deposition is deposited through an atomic layer deposition process, wherein the depositing the oxide deposition causes a non-uniform removal of some of the carbon based deposition. At least one additional process is provided, wherein the at least one additional process completes formation of features over the wafer, wherein the features are more uniform than features that would be formed without pretuning.

Abstract: A wafer support structure in a chamber of a semiconductor manufacturing apparatus is provided. The wafer support structure includes a dielectric block having a bottom surface and a top surface supports a wafer when present. The wafer support structure includes a baseplate for supporting the dielectric block. The wafer support structure includes a first electrode embedded in an upper part of the dielectric block. The first electrode is proximate and below the top surface of the dielectric block. A top surface of the first electrode is substantially parallel to the top surface of the dielectric block. The first electrode is configured for connection to a direct current (DC) power source. The wafer support structure includes a second electrode embedded in the dielectric block. The wafer support structure includes a second electrode disposed below the first electrode and a separation distance is defined between the first electrode and the second electrode within the dielectric block.

Abstract: A method for forming a stair-step structure in a stack on a substrate is provided. The method comprises at least one stair step cycle. Each stair step cycle comprises trimming the mask and etching the stack. Etching the stack is provided in a plurality of cycles wherein each cycle comprises etching a SiO2 layer and etching a SiN layer. Etching a SiO2 layer comprises flowing a SiO2 etching gas into the plasma processing chamber, wherein the SiO2 etching gas comprises a hydrofluorocarbon, an inert bombardment gas, and at least one of SF6 and NF3, generating a plasma from the SiO2 etching gas, providing a bias, and stopping the SiO2 layer etch. The etching a SiN layer comprises flowing a SiN etching gas into the plasma processing chamber, comprising a hydrofluorocarbon and oxygen, generating a plasma from the SiN etching gas, providing a bias, and stopping the SiN layer etch.

Abstract: Methods for depositing films by atomic layer deposition using aminosilanes are provided.

Abstract: Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO2 and SiN can be selectively etched using a plasma formed in an Hz-containing process gas. The etching creates a recessed feature in place of the tin oxide between the surrounding materials. A third material, such as SiO2 is deposited over the resulting recessed feature without fully filling the recessed feature, forming an air gap. A method for selectively etching tin oxide in a presence of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, or SiCN, includes, in some embodiments, contacting the substrate with a plasma formed in a process gas comprising at least about 50% Hz. Etching of tin oxide can be performed without using an external bias at the substrate and is preferably performed at a temperature of less than about 100° C.

Abstract: Disclosed are apparatuses and methods for performing atomic layer etching. A method may include modifying one or more surface layers of material on the substrate and exposing the one or more modified surface layers on the substrate to an electron source thereby removing, without using a plasma, the one or more modified surface layers on the substrate. An apparatus may include a processing chamber, a process gas unit, an electron source, and a controller with instructions configured to cause the process gas unit to flow a first process gas to a substrate in a chamber interior, the first process gas is configured to modify one or more layers of material on the substrate, and to cause the electron source to generate electrons and expose the one or more modified surface layers on the substrate to the electrons, the one or more modified surface layers being removed, without using a plasma.

Abstract: In various examples, the disclosed subject matter includes a substrate pedestal that includes a platen formed from a ceramic material and having an upper surface to support a substrate during processing. A stem, formed from a ceramic material, has an upper-stem flange upon which the platen is mechanically coupled. The stem has an interior portion. A backside gas-delivery tube, formed from a ceramic material, is located in the interior portion of the stem. The backside gas-delivery tube includes an upper gas-tube flange that is located between a lower surface of the platen and an upper surface of the upper-stem flange. The backside gas-delivery tube is in fluid communication with at least one backside-gas passage of the platen and is arranged to supply a backside gas to a region below a lower surface of the substrate during processing. Other examples of apparatuses and methods of making and using the apparatuses are included.

Abstract: The invention relates to a filter for filtering particles from a plasma plume. The filter includes a housing with two pass-through openings arranged in the housing wall and forming a pass-through channel for passing at least part of the plasma plume through the housing, which pass-through channel extends from one side of the housing to an opposite side of the housing, at least one primary blade arranged at a distance from and rotatable around a rotation axis, which rotation axis is parallel and spaced apart from the center line of the pass-through channel, with the path of the at least one primary blade intersecting with the pass-through channel and with the at least one primary blade having a contact surface for contact with the plasma plume, which contact surface is facing in the direction of the rotation direction, and a drain channel connecting to a drain opening arranged in the housing wall.

Abstract: Computer implemented methods and computer program products have instructions for generating transfer functions that relate segments on lithography photomasks to features produced by photolithography and etching using such segments. Such methods may be characterized by the following elements: (a) receiving after development inspection metrology results produced from one or more first test substrates on which resist was applied and patterned using a set of design layout segments; (b) receiving after etch inspection metrology results produced from one or more second test substrates which were etched after resist was applied and patterned using said set of design layout segments; and (c) generating the transfer function using the set of design layout segments together with corresponding after development inspection metrology results and corresponding after etch inspection metrology results.

Abstract: A system includes an electrode. The electrode includes a showerhead having a first stem portion and a head portion. A plurality of dielectric layers is vertically stacked between the electrode and a first surface of a conducting structure. The plurality of dielectric layers includes M dielectric layers arranged adjacent to the head portion and P dielectric portions arranged around the first stem portion. The plurality of dielectric layers defines a first gap between the electrode and one of the plurality of dielectric layers, a second gap between adjacent ones of the plurality of dielectric layers, and a third gap between a last one of the plurality of dielectric layers and the first surface. A number of the plurality of dielectric layers and sizes of the first gap, the second gap, and the third gap are selected to prevent parasitic plasma between the first surface and the electrode.