Abstract: A polishing head for use in an apparatus for chemically-mechanically polishing semiconductor wafers is provided. The polishing head includes a first side having at least a portion thereof operably connectable with a spindle on the apparatus; and a second side opposite the first side, the second side having a substantially spherical cap shape comprising an outer region adapted to apply a first force onto a semiconductor wafer against a polishing pad, and an inner region adapted to apply a second force onto the semiconductor wafer against the polishing pad, the second force being different from the first force, whereby the first force and the second force cause the polishing pad to planarize the semiconductor wafer substantially uniformly. A method of polishing semiconductor wafers is also provided.

Abstract: A system, method and apparatus for cleaning a substrate edge includes a substrate supporting device for substantially supporting a substrate in a selected plane. The substrate has a circular shape, a circumferential edge, a front side and a back side. The edge has a bevel shaped cross-section. The substrate edge cleaning apparatus also includes a first edge cleaning roller that has an open curved scrubbing surface in contact with at least part of a first portion the edge of the substrate. An interaction of the first edge cleaning roller with the part of the first portion can also be adjusted dynamically.

Abstract: An apparatus is provided for producing a wet region and corresponding dry region on a wafer. A proximity brush unit delivers fluids with a rotatable brush to produce the wet region on the wafer. As the proximity brush unit moves in a selected scan method across the wafer, a plurality of ports produces the dry region on the wafer. Further, the rotatable brush disposed within the proximity brush unit can rotate via mechanical gears or electromagnetic levitation. The selected scan method that produces the wet region and the dry region moves the proximity brush unit in a variety of methods including a radial scan, a linear scan, a spiral scan and a raster scan. To further produce a dry region during the selected scan method, the plurality of ports disposed on the surface of the proximity brush unit is on the trailing edges of the proximity head unit and the wafer.

Abstract: A apparatus for drying a substrate includes a vacuum manifold positioned adjacent to an edge wheel. The edge wheel includes an edge wheel groove for receiving a peripheral edge of a substrate, and the edge wheel is capable of rotating the substrate at a desired set velocity. The vacuum manifold includes a proximity end having one or more vacuum ports defined therein. The proximity end is positioned at least partially within the edge wheel groove, and using supplied vacuum removes fluids that accumulate in the edge wheel groove and prevents re-deposit of trapped fluids around the peripheral edge of the substrate.

Abstract: An apparatus for use in processing a substrate includes a brush enclosure extending over a length. The brush enclosure is configured to be disposed over a surface of the substrate and has an open region that is configured to be disposed in proximity to the substrate. The open region extends over the length of the brush enclosure and enables foam from within the brush enclosure to contact the surface of the substrate. A substrate cleaning system and method for cleaning a substrate are also described.

Abstract: An edge wheel assembly for use in a semiconductor wafer fabrication brush box is provided. The edge wheel assembly is configured to support and to rotate a semiconductor wafer in a vertical orientation and includes an edge wheel assembly block having at least two pairs of edge wheel shaft bores. Edge wheels are attached to shafts extending through the edge wheel shaft bores, and a drive motor drives the shafts to rotate the edge wheels. The drive motor is coupled to the edge wheel assembly block with a plate which is designed to enable insertion of the edge wheel assembly into either one of a first side and a second side of the brush box. Component parts are designed to be configurable to a plurality of orientations and implementations.

Abstract: CMP methods in which a polishing pad is moved relative to a wafer and a retainer ring implement instructions for applying required pressure to the wafer for CMP operations. Accuracy of computations of the pressures, and of conversion of the pressure to force, is improved without use of high resolution components, such as high resolution digital devices. Such improved accuracy is achieved using both digital and analog operations, and by converting values of required pressure or force from one set of units to a second set of units and then back to the first set of units. A quantization process is performed using data processed by average resolution digital devices. The process transfers both pressure/force scale and pressure/force set point data between separate processors to obtain computed values of pressure and force having acceptable accuracy, such that quantization errors are eliminated or significantly reduced.

Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

Abstract: A method for controlling a plasma etch process while etching a layer stack having a first layer disposed above an end-point generating layer is disclosed. The method includes etching through the first layer and at least partially through the end-point generating layer while monitoring an absorption rate of a light beam traversing an interior portion of the plasma processing chamber, wherein the end-point generating layer is selected from a material that produces a detectable change in the absorption rate when etched. The end-point generating layer is characterized by at least one of a first characteristic and a second characteristic. The first characteristic is an insufficient thickness to function as an etch stop layer, and the second characteristic is an insufficient selectivity to etchants employed to etch through the first layer to function as the etch stop layer. The method additionally includes generating an end-point signal upon detecting the detectable change.

Abstract: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

Abstract: A bias compensation self-aligned contact (SAC) etch endpoint detecting system is provided. The system includes an etch reactant chamber, an ESC power supply, and a signal processing computer. The etch reactant chamber includes an electrostatic chuck (ESC), a top electrode, and a bottom electrode. The ESC supports a substrate having an interlevel dielectric (ILD) layer to be etched. The ESC power supply is coupled to the ESC and is configured to function as a bias compensating power supply. The signal processing computer monitors a bias compensation signal generated by the ESC power supply. The etch process to be carried out in the etch reactant chamber is configured to be discontinued when the bias compensation signal is determined to have a previously ascertained characteristic evidencing an etch endpoint of the ILD layer.

Abstract: Broadly speaking, the present invention provides a method and an apparatus for planarizing a semiconductor wafer (“wafer”). More specifically, the present invention provides for depositing a planarizing layer over the wafer, wherein the planarizing layer serves to fill recessed areas present on a surface of the wafer. A planar member is positioned over and proximate to a top surface of the wafer. Positioning of the planar member serves to entrap electroless plating solution between the planar member and the wafer surface. Radiant energy is applied to the wafer surface to cause a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase in turn causes plating reactions to occur at the wafer surface. Material deposited through the plating reactions forms a planarizing layer that conforms to a planarity of the planar member.

Abstract: An antenna includes excitation terminals responsive to an RF source to supply an RF electromagnetic field to a plasma that processes a workpiece in a vacuum chamber. The coil includes a transformer having a primary winding coupled to the excitation terminals and a multi-turn plasma excitation secondary winding connected in series with a capacitor.

Abstract: Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer (“wafer”). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to the wafer surface. The selective heating of the wafer surface causes a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase at the interface in turn causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source.

Abstract: A cylindrical pump baffle fitted to a semiconductor processing chamber is disclosed. The pump baffle contains a screen with bores therethrough to allow process gasses from the process chamber to be exhausted from the chamber at a reduced rate. This decreases process discrepancies to the wafer due to the prejudice of gas concentration as a result of the pressure differential imposed upon the gas and thereby the wafer brought about by the rapid and relatively unimpeded exit flow of process gasses when no restrictive member is in place. The pump baffle is also machined such that it does not block the placement and removal of wafers by the platform robot arm.

Abstract: A capacitive manometer includes a flow passage through which gas can enter the manometer, a deflectable diaphragm, and a filter arranged in the flow passage. The filter is capable of removing condensable vapors from the gas so that the condensable vapors do not reach and deposit on the diaphragm. The capacitive manometer can include a cooling unit arranged to cool the filter so as to enhance removal of condensable vapors from the gas by the filter. The capacitive manometer can include a baffle having gas passages distributed to control distribution of condensable vapors, which pass through the baffle, on the diaphragm.

Abstract: A chemical mechanical polishing (CMP) apparatus is provided. The CMP apparatus includes a first roller situated at a first point and a second roller situated at a second point. The first point is separate from the second point. Also included in the apparatus is a polishing pad strip having a first end secured to the first roller and a second end secured to the second roller. The first roller and the second roller are configured to reciprocate so that the polishing pad strip oscillates at least partially between the first point and the second point.

Abstract: A method and apparatus for conditioning a polishing pad is described. The method includes applying a stream of pressurized liquid to the polishing pad, and removing a significant amount of slurry and liquid from the polishing pad using a vacuum. The apparatus includes a liquid distribution unit forming at least one opening upon which liquid is forced through at high pressure, the opening directed at the polishing pad, and a liquid recovery unit positioned downstream from the liquid distribution unit and in communication with the polishing pad, the liquid recovery unit connected with a vacuum for removing liquid and slurry from the polishing pad.

Abstract: A system for processing a wafer includes a cleaning module configured to only clean the back side of the wafer so as to remove unwanted particles therefrom before performing subsequent processing tasks on the process side of the wafer. The system also includes a processing module configured to perform processing tasks on the process side of the wafer. The processing module includes a chuck for supporting the wafer during the processing task. The system further includes a transport module configured to remove the cleaned wafer from the cleaning module, move it to the processing module and place it on the chuck of the processing module without performing any intervening manipulations during the movement.

Abstract: Apparatus and methods are disclosed that promote greater polishing uniformity in linear CMP systems by introducing a relative lateral motion between a CMP belt and a rotating polish head securing a wafer. A belt polish module comprises a linear CMP belt forming a loop around an idle roller and a drive roller, first and second pistons engaging, respectively, first and second ends of the idle roller, and a controller configured to vary the forces applied by the first and second pistons to the ends of the idle roller in order to laterally translate the linear CMP belt. A method for linear CMP comprises rotating a wafer about a vertical axis, contacting the rotating wafer against a linear CMP belt moving in a longitudinal direction, and causing a relative lateral motion between the rotating wafer and the linear CMP belt.