Patents Assigned to Lapis Semiconductor Co., Ltd.
  • Patent number: 10417545
    Abstract: A detection device includes a first antenna configured to receive a first radio wave transmitted from an external device, a second antenna configured to receive the first radio wave transmitted from the external device, and transmit a second radio wave to the external device; and a chip configured to obtain a comparison result between a first electromotive force generated by the first radio wave received by the first antenna and a second electromotive force generated by the first radio wave received by the second antenna, and to send the comparison result to the external device through the second radio waive. When the first antenna is disposed closer than the second antenna to a place where the existence of moisture is to be detected, a change of the first electromotive force is greater than a change of the second electromotive force in response to the existence of moisture.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: September 17, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Daisuke Oda
  • Patent number: 10411715
    Abstract: A semiconductor device includes an oscillator that oscillates at a specific frequency, a semiconductor integrated circuit that integrates a temperature sensor that detects a peripheral temperature, and a controller that is electrically connected to the oscillator and that corrects temperature dependent error in the oscillation frequency of the oscillator based on the temperature detected by the temperature sensor and a sealing member that integrally seals the oscillator and the semiconductor integrated circuit.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: September 10, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Kazuya Yamada, Toshihisa Sone, Akihiro Takei, Yuichi Yoshida, Kengo Takemasa
  • Patent number: 10410595
    Abstract: First to N-th latches capture N pieces of pixel data indicative of the luminance levels of respective pixels in synchronization with first to N-th capture clock signals each having different edge timing. Voltages corresponding to the pieces of pixel data output from the first to N-th latches are applied to each of the data lines of the display device. In this case, first to N-th flip-flops formed in an N-stage shift register capture a single pulse load signal which is synchronized with a horizontal synchronizing signal in a video signal while sequentially shifting the load signal to subsequent stages in synchronization with a reference timing signal supplied from the outside. Outputs of the first to N-th flip-flops in the N-stage shift register are supplied as first to N-th capture clock signals, to the first to N-th latches, respectively.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: September 10, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroaki Ishii
  • Patent number: 10401434
    Abstract: A semiconductor device including plural first switches, each provided so as to correspond to one of plural battery cells connected in series, each first switch including one end connected to a corresponding battery cell and another end connected to one electrode of a corresponding charge storage section of plural charge storage sections, each of the charge storage sections being provided so as to correspond to one of the plural battery cells, and another electrode of each charge storage section being connected to a fixed potential; plural second switches, each provided so as to correspond to one of the plural first switches, each second switch including one end connected to the other end of the corresponding first switch; and processing section connected to each other end of the plural second switches, that processes voltages supplied via the second switches.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: September 3, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hisao Ohtake, Naoaki Sugimura
  • Publication number: 20190265784
    Abstract: An operation determination device that determines a change in the facing direction of a user's face as a contact-free operation on a display image includes an image acquisition unit that acquires a captured image that is captured of the user's face and an image processing unit that performs image processing on the captured image and detects the direction of the user's face. The image processing unit includes a first processing unit that detects a portion of the user's face in the captured image and a second processing unit that determines the direction of the user's face in relation to a display surface that displays the display image, on the basis of the portion of the user's face detected in the captured image. The first processing unit includes hardware that executes specific detection processes, and the second processing unit includes one or more processors executing software that execute processes according to output from the first processing unit.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 29, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroji AKAHORI
  • Publication number: 20190267101
    Abstract: A serial interface circuit, a semiconductor device, and a serial-parallel conversion method are provided. The disclosure is to generate first to nth timing signals respectively indicating timings that differ by 1 bit cycle of the bit string when receiving a serial signal including the bit string in a serial form and converting the bit string into a parallel form to obtain a parallel bit group. Each bit in the bit string is held at the timings of the first to tth timing signals as the standby bit group, the standby bit group is acquired at the timing of any one of the (t+1)th to nth timing signals as a part of the parallel bit group, and each bit in the bit string is held at the timings of the (t+1)th to nth timing signals and the held bit group is set as another part of the parallel bit group.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 29, 2019
    Applicant: LAPIS SEMICONDUCTOR CO., LTD
    Inventor: Tatsuru Shinoda
  • Patent number: 10396793
    Abstract: A level shift circuit includes: a constant-current generation unit; a current mirror unit that flows the constant-current through first and second lines; and a level shift unit that receives first and second input signals, the first input signal being varied between first and second logic levels and having first and second potentials at the first and second logic levels respectively, the second input signal being a phase-inverted signal of the first input signal, the level shift unit producing first and second output signals that are acquired by shifting a signal level at the first logic level of the first and second input signals from the first potential to the power supply potential, the level shift unit outputting the first output signal from a node on the second line and outputting the second output signal from a node on the first line. The constant-current generation unit includes a current adjustment circuit which varies the constant current value depending on a variation in the first potential.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: August 27, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Shuji Furuichi
  • Patent number: 10396572
    Abstract: A power transmission device includes: a power reception unit that receives electric power from outside; a power transmission line that transmits the electric power received with the power reception unit to a battery; a transmission cut-off switch that cuts off the power transmission line, a transmission control circuit that uses the electric power received in the power reception unit as operation power, receives a battery state signal indicating a state of the battery, and switches conduction and non-conduction of the transmission cut-off switch on the basis of the battery state signal; and a cut-off control circuit that monitors the received electric power from the power reception unit by receiving electric power from the battery, and forcibly puts the transmission cut-off switch in a non-conductive state when the received electric power is less than a specified value.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 27, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Takashi Taya
  • Publication number: 20190259334
    Abstract: Only once every N horizontal scanning periods, correction processing for providing a correction voltage for correcting a characteristic of a drive transistor for driving a light-emitting element formed in a display device to data lines of the display device and display driving processing for sequentially providing, to the data lines of the display device, gradation voltages for one horizontal scanning line based on a video signal corresponding to each of N horizontal scanning lines are executed.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Shouji NITAWAKI
  • Publication number: 20190261507
    Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 22, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Kentaro TODA, Kenji ARAI, Manabu MIYAZAWA, Kenichiro NAGATOMO, Toru UENO, Tsuguto MARUKO, Hirofumi OGAWA, Tetsuo OOMORI
  • Patent number: 10388339
    Abstract: A semiconductor memory device and a data reading method capable of appropriately reading data stored in memory cells are provided. The semiconductor memory device includes: a memory cell array including multiple memory cells and having a known-data storage area storing determination data used for determining appropriateness or inappropriateness of a value of each of a reading voltage applied to a memory cell when reading data stored in the memory cell and a comparative current used for a comparison with a current flowing through a memory cell according to stored data; a decoder that applies the reading voltage to a memory cell to be read according to an address representing the memory cell to be read; and a sense amplifier including a comparison circuit that outputs a comparison result acquired by comparing a current flowing through the memory cell to be read 66 according to stored data with the comparative current.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: August 20, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Tatsuru Shinoda
  • Patent number: 10388209
    Abstract: An interface circuit for supplying a plurality of data signals to a data reception circuit includes a timing signal generating circuit configured to generate a timing signal. The timing signal indicates a timing to switch operation of the interface circuit between a data input mode and a non-input mode. The interface circuit further includes a data control circuit configured to control a supply of the data signals to the data reception circuit in the data input mode, a plurality of abnormality detection circuits each configured to detect an abnormality that has occurred in the data reception circuit, and a select circuit configured to select one abnormality detection circuit based on each of the data signals supplied in the non-input mode of the interface circuit, and output, as an abnormality detection signal, a detection result of the selected one of the abnormality detection circuits.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 20, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Daisuke Kadota
  • Patent number: 10381062
    Abstract: A non-volatile semiconductor storage device including a first potential retention line configured to retain a potential corresponding to data read from the memory cell, a second potential retention line configured to retain a reference potential read from the memory cell in which the reference potential is written after the data is read out, a sense amplifier configured to amplify a difference between the potential retained by the first potential retention line and the reference potential for reading out the data from the memory cell, a first offset adjustment circuit connected to the first potential retention line, for adjusting an offset for the potential, a second offset adjustment circuit connected to the second potential retention line, and an offset command signal supply circuit configured to supply a first offset command signal to the first offset adjustment circuit so as to control the offset.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: August 13, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Takashi Yamada
  • Patent number: 10381864
    Abstract: A semiconductor device includes a first signal outputting portion; a second signal outputting portion; and a voltage outputting portion. The first signal outputting portion compares a first voltage output from a first power source and a second voltage output from a second power source, and to output a comparison result. The second signal outputting portion determines whether the second voltage is greater than a threshold voltage, and to output a determination result. The voltage outputting portion outputs the second voltage from an output terminal when the second voltage is greater than the threshold voltage. Further, the voltage outputting portion outputs one of the first voltage and the second voltage from the output terminal when the second voltage is smaller than the threshold voltage.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 13, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Kouhei Tanaka
  • Patent number: 10375819
    Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: August 6, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Kentaro Toda, Kenji Arai, Manabu Miyazawa, Kenichiro Nagatomo, Touru Ueno, Tsuguto Maruko, Hirofumi Ogawa, Tetsuo Oomori
  • Patent number: 10374469
    Abstract: The present disclosure provides a wireless power receiver including: a power receiver configured to receive electrical power that is wirelessly transmitted from a wireless power transmitter; a power reception-side communication section configured to wirelessly communicate with the wireless power transmitter; a storage section to which data received by the power reception-side communication section is written by using the electrical power received by the power transmitter; and a monitoring section configured to monitor the electrical power or a voltage that corresponds to the electrical power supplied to the storage section in a case in which the data is being written to the storage section, the monitoring section transmits write information, which indicates whether or not the data was correctly written to the storage section based on a monitoring result, from the power reception-side communication section to the wireless power transmitter information.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 6, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroji Akahori, Takashi Taya
  • Publication number: 20190237012
    Abstract: A display driving device comprising: a high supply voltage operation unit that generates an operating current under application of a high supply voltage so as to supply driving voltages to a display panel; a low supply voltage operation unit that operates under the application of a low supply voltage lower than the high supply voltage and controls the high supply voltage operation unit; and a reuse circuit that receives the operating current from the high supply voltage operation unit and supplies the operating current to a ground side via the low supply voltage operation unit so as to apply the low supply voltage to the low supply voltage operation unit.
    Type: Application
    Filed: April 25, 2018
    Publication date: August 1, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroyoshi ICHIKURA, Hiroki AIZAWA, Takeshi NOSAKA
  • Patent number: 10366764
    Abstract: Provided is a sense amplifier circuit for detecting data having been read from a memory cell. The sense amplifier circuit includes: a potential control unit for controlling the potential of a bit line connected to a memory cell; a current amplifier unit for amplifying a readout current flowing from the memory cell to the bit line so as to produce an amplified current; and a detection unit for detecting data having been read from the memory cell on the basis of the amplified current. The potential control unit controls the potential of the bit line in a data readout duration, and the data readout duration includes a current amplification duration, and the current amplifier unit amplifies the readout current in the current amplification duration.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 30, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Masayuki Otsuka
  • Patent number: 10365306
    Abstract: A detection circuit, provided in a gamma buffer circuit that includes at least one transistor that receives the application of a first voltage and generates gradation voltages on the basis of a plurality of gamma voltages, includes: a first comparison circuit that compares the largest gamma voltage with a substrate potential of the transistor and outputs a first comparison result signal, a second comparison circuit that includes an inverter which is operable under a second voltage as a source voltage, compares a threshold voltage of the inverter with the substrate potential, and outputs a second comparison result signal; and a detection result output circuit for outputting a detection result showing if the voltage decrease or power discontinuity of the first voltage is occurring on the basis of the first comparison result signal and the second comparison result signal.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: July 30, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Toshimi Yamada
  • Publication number: 20190229107
    Abstract: The disclosure provides a semiconductor device that can reduce the area of the circuit elements formed thereon. The semiconductor device includes a first conductivity type region formed on a substrate and formed with a resistance element surrounded by an insulating film; a second conductivity type region laminated in contact with an upper surface of the resistance element; a capacitor formed on the resistance element via an interlayer insulating layer; a via electrically connecting a terminal of the resistance element and a terminal of the capacitor in series; and a power supply line and a ground line electrically connected to the other terminal of the resistance element and the other terminal of the capacitor respectively.
    Type: Application
    Filed: January 22, 2019
    Publication date: July 25, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Chikashi Fuchigami