Abstract: A semiconductor device includes a first semiconductor chip and a second semiconductor chip connected to each other. The first semiconductor chip includes a first alignment mark and a second alignment mark composed of conductors electrically isolated from each other, and a first terminal and a second terminal electrically connected to the first alignment mark and the second alignment mark. The second semiconductor chip includes a guard ring including an annular conductor provided along an outer edge of the second semiconductor chip, and a third alignment mark and a fourth alignment mark composed of conductors electrically connected to the guard ring. The first semiconductor chip and the second semiconductor chip are connected such that the first alignment mark and the third alignment mark overlap with each other, and the second alignment mark and the fourth alignment mark overlap with each other.

Abstract: A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.

Abstract: Provided is a semiconductor device that can suppress flash/burrs from forming on a lower surface of a die pad in a configuration in which the lower surface of the die pad is exposed from a sealing resin. The semiconductor device includes a lead frame, a semiconductor chip, and a sealing body. The lead frame includes a plate-shaped die pad and a lead. The die pad has one principal surface with a mounting region for mounting the semiconductor chip. The die pad includes a side portion and a frame-shaped protrusion on the side portion in top view. The protrusion overhangs in a lateral direction in an eave shape along the one principal surface. The semiconductor chip is mounted on the mounting region. The sealing body covers a side surface of the die pad while exposing the other principal surface of the die pad and sealing the semiconductor chip on the one principal surface of the die pad. The sealing body holds the die pad and the lead.

Abstract: There is provided a semiconductor device including: a first substrate and a second substrate mounted in an overlapping manner, wherein the first substrate includes: plural conductive first pads that are arranged on a substrate surface of the first substrate at intervals; plural conductive second pads that are arranged on the substrate surface at intervals; and a conductive member, and the second substrate includes: plural conductive third pads; plural conductive fourth pads; a first measurement pad that is measures whether or not the third pad is conductive with the fourth pad; and a second measurement pad that is checks whether or not the third pad is conductive with the fourth pad.

Abstract: A semiconductor device includes: a supporting body having first and second principal faces, and semiconductor elements; a thin film metal electrode on the first principal face; a thick film metal body on the thin film metal electrode; and a resin structure on the supporting body. The thick film metal body has a thickness greater than that of the thin film metal electrode. The resin structure includes a first resin body that covers a side of the thick film metal body. The resin structure has at least one of structures 1 and 2 as follows: in the structure 1, the resin structure further includes a second resin body on the second principal face; and in the structure 2, the first resin body includes first and second regions on the first principal face, and the second region has a thickness greater than that of the first region.

Abstract: A semiconductor device including: a semiconductor substrate; a seed layer that is formed on the semiconductor substrate; and wiring that is formed on the seed layer and includes parallel row portions that are arranged at intervals from each other, and in which penetration passages that penetrate the parallel row portions in a direction in which the parallel rows lined up are formed in the parallel row portions.

Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, a post electrode, and a burying layer. The first semiconductor chip includes a plurality of first metal terminals and external metal terminals formed in different regions, and a bonding layer including an oxide film to fill therebetween. The second semiconductor chip includes a plurality of second metal terminals formed on an opposed surface of the first semiconductor chip and a bonding layer including an oxide film provided to fill therebetween. The second semiconductor chip is mounted on the first semiconductor chip by bonding the bonding layers one another. The post electrode is formed above the one surface of the first semiconductor chip and provided on the external metal terminal of the first semiconductor chip. The burying layer buries the second semiconductor chip and the post electrode on the one surface of the first semiconductor chip.

Abstract: A multilayer substrate includes a first dielectric layer, a first conductive layer, and a conductor portion. The first dielectric layer has a first region. The first conductive layer is laminated on the first dielectric layer, excluding the first region. The conductor portion has one or more auxiliary conductors disposed at a distance from the first conductive layer, and one or more connecting conductors that connect said one or more auxiliary conductors to the first conductive layer.

Abstract: A semiconductor device includes a thin-film metal electrode provided on a first main surface of a support base, a thin-film resin layer covering an edge of the thin-film metal electrode, a thick-film metal body located above the thin-film metal electrode and containing copper, a thick-film resin body covering a lateral surface of the thick-film metal body, and a structure body including at least one of a first film provided on the first main surface and a second film provided on a second main surface. The thick-film metal body, the thin-film metal electrode, and the support base are arranged along a direction of a first axis. Upper surfaces of the thick-film metal body and the thick-film resin body extend along a reference plane intersecting with the first axis. A thermal expansion coefficient of the first film is between those of the thick-film resin body and a semiconductor of the support base.

Abstract: A display driving device includes a high voltage operating unit obtaining an operating current according to the application of the high power supply voltage from the first voltage application line; a low voltage operating unit that operates according to an application of a low power supply voltage to control the high voltage operating unit; a recycling circuit that receives the operating current from the high voltage operating unit via a relay coupling line and applies the low power supply voltage to the low voltage operating unit while supplying the received operating current to a reference potential line via the low voltage operating unit; and a current bypass circuit that flows a part of the operating current flowing through the relay coupling line into the reference potential line without supplying the part of the operating current to the recycling circuit according to a voltage increase in the low power supply voltage.

Abstract: A semiconductor device includes a semiconductor substrate and a first memory cell disposed on the semiconductor substrate. The first memory cell includes a first write and erasure transistor, a first read transistor, and a first charge transfer reduction transistor. The first write and erasure transistor controls data writing and erasing. The first read transistor controls data reading. The first charge transfer reduction transistor reduces injection of an electric charge to the first write and erasure transistor and the first read transistor.

Abstract: A foundation portion and a conductive base portion disposed on the foundation portion are formed on a temporary support, a semiconductor element electrically connected to the base portion is disposed on a side of the temporary support on which the foundation portion and the base portion are formed, and an insulating layer coming into a state of burying the foundation portion, the base portion, and the semiconductor element is formed on the temporary support. Subsequently, surfaces of the foundation portion and the insulating layer on a side of the temporary support are exposed by removing the temporary support, and the exposed foundation portion is further removed, thereby disposing the base portion in a state of being more recessed than the surface of the insulating layer. An external connection terminal is formed on the exposed base portion to manufacture the semiconductor package.

Abstract: A semiconductor device in which an SOI substrate having an element region in which circuit elements are formed, an insulation layer having a first surface adjoining the SOI substrate, and a support substrate of a first conductivity type are laminated. On the SOI substrate, a transfer electrode configured to transfer charges generated in the support substrate to a third semiconductor layer is formed in a region different from the element region, and the transfer electrode and the third semiconductor layer are adjacent in plan view.

Abstract: A semiconductor device includes a semiconductor chip, a first antenna element and a second antenna element. The semiconductor chip includes a communication circuit. The first antenna element includes a line pattern which is electrically connected to the communication circuit and meanderingly reciprocates in a first direction parallel to a first surface of the semiconductor chip. The second antenna element includes a line pattern which is electrically connected to the communication circuit and meanderingly reciprocates in a second direction parallel to a second surface opposite to the first surface of the semiconductor chip.

Abstract: A semiconductor device including: a first semiconductor layer having a first conductive type; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a second conductive type that is a conductive type different from the first conductive type; an impurity region of the first conductive type formed at a surface of the second semiconductor layer; first electrodes contacting the impurity region, the second semiconductor layer, and the first semiconductor layer via a first insulating film; and second electrodes contacting the first electrodes via a second insulating film, and contacting the first semiconductor layer via a third insulating film, the second electrodes including PN junctions at borders between upper portions that contact the first semiconductor layer via the third insulating film and lower portions that contact the first semiconductor layer via the third insulating film.

Abstract: A voltage generation unit includes first to k-th amplifiers that individually receiving first to k-th reference voltages having mutually different voltage values, individually amplify these reference voltages with gain 1, and output the reference voltages. The generation unit generates plural gradation voltages by dividing voltages between respective voltages output from the first to k-th amplifiers. A decoder unit selects one gradation voltage corresponding to the luminance level represented by the pixel data piece among the gradation voltages and generates a signal having the one gradation voltage as the drive signal for driving a display device. Each amplifier includes a response-speed increase circuit that includes at least one transistor in which a source and a back gate are connected to an output terminal of the amplifier, a predetermined electric potential is applied to a drain, and the reference voltage received by the amplifier is received at a gate.

Abstract: A display driver according to the present invention generates a plurality of driving voltages based on a video signal and applies the respective driving voltages to a plurality of source lines of a display panel. The display driver includes an overdrive part and an overdrive control circuit. The overdrive part executes an overdrive processing to increase amplitudes of the driving voltages. The overdrive control circuit detects an internal temperature of the display driver and stops the overdrive processing by the overdrive part when the temperature is higher than a predetermined temperature threshold.

Abstract: A battery monitoring system includes a first group of a plurality of battery cells connected in series and including a first battery cell at a highest potential and a second battery cell at a lowest potential; a second group of a plurality of battery cells connected in series and including a third battery cell at a highest potential and a fourth battery cell at a lowest potential, the second group of the battery cells being connected to the first group of the battery cells in series; and first and second semiconductor devices capable of measuring a voltage of the first group of the battery cells and a voltage of the second group of the battery cells, respectively.

Abstract: A semiconductor device includes a semiconductor chip, a first antenna element and a second antenna element. The semiconductor chip includes a communication circuit. The first antenna element includes a line pattern which is electrically connected to the communication circuit and meanderingly reciprocates in a first direction parallel to a first surface of the semiconductor chip. The second antenna element includes a line pattern which is electrically connected to the communication circuit and meanderingly reciprocates in a second direction parallel to a second surface opposite to the first surface of the semiconductor chip.

Abstract: The present invention generates data series indicating respective combined-wave data pieces by a first step of obtaining a reference time length as a reference of a time length of one combined wave, a sampling interval time, and a frequency fluctuation rate, a second step of calculating a total number of samples in the data series indicating the one combined wave on the basis of the reference time length, the sampling interval time, and the frequency fluctuation rate, a third step of calculating a rotation angle with respect to the sampling interval time on the basis of the total number of samples for each of plural sound data pieces, a fourth step of calculating combined values for the total number of samples, the combined values being obtained by combining respective values of the plural sound data pieces, the values being calculated on the basis of the rotation angles for the respective sampling interval times, a fifth step of generating a series of the combined values for the total number of samples for t