Patents Assigned to Lapis Semiconductor Co., Ltd.
  • Patent number: 11961921
    Abstract: A semiconductor device has a semiconductor substrate and a semiconductor film doped with impurities that is formed so as to cover an inner wall surface of a trench formed so as to extend from a first surface of the semiconductor substrate towards an interior thereof. The semiconductor film is formed so as to extend continuously from the inner wall surface to the first surface of the semiconductor substrate. The semiconductor device further has an opposite electrode having a first portion that is provided at a position opposing the semiconductor substrate while sandwiching the semiconductor film therebetween, and that extends on the first surface of the semiconductor substrate, and a second portion that is continuous with the first portion and extends so as to fill the trench. The semiconductor device further has an insulating film that insulates the semiconductor film from the opposite electrode.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: April 16, 2024
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroshi Shibata
  • Publication number: 20240105565
    Abstract: A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Toshihisa SONE, Kazuya YAMADA, Akihiro TAKEI, Yuichi YOSHIDA, Kengo TAKEMASA
  • Patent number: 11929432
    Abstract: A semiconductor device including a source region formed at one main face of a semiconductor substrate; a drain region formed at the one main face and connected to the source region through a channel region; a gate electrode formed above the channel region; a drift layer formed at the one main face at a position between a lower portion of the gate electrode and the drain region; a trench including an opening in which one end is at the lower portion of the gate electrode and another end is at a position adjacent to the drain region, the trench being formed in the semiconductor substrate at a predetermined depth from the one main face to cut vertically across the drift layer; and an electrical field weakening portion, provided at vicinity of the one end, that weaken an electrical field generated between the source region and the drain region.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 12, 2024
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Kazuya Uda
  • Patent number: 11921577
    Abstract: The disclosure provides a semiconductor storage element which is provided with an error detection and correction circuit and, when an uncorrectable error occurs in the semiconductor storage element, capable of promptly transferring the occurrence to the outside, and provides a semiconductor storage device and a system-on-chip using the same. The semiconductor storage element includes a storage part storing data, an error detection and correction part detecting an error in the data stored in the storage part and correcting the error if possible, a monitoring part issuing an uncorrectable error signal when an uncorrectable error occurs in the error detection and correction part, and a terminal transmitting the uncorrectable error signal to the outside.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: March 5, 2024
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Kota Ama, Tetsuya Tanabe
  • Patent number: 11907003
    Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: February 20, 2024
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Kenjiro Matoba, Kazuhiro Yamashita
  • Patent number: 11894447
    Abstract: A method for manufacturing a semiconductor device includes: implanting a P-type impurity from a region where the first conductor film is formed toward an inside of the semiconductor substrate with a first acceleration energy; forming a nitride film provided with a first opening on the first conductor film; forming an insulating film with a second opening from which the first conductor film is exposed; forming a second conductor film to fill the second opening of the insulating film; removing the nitride film and a portion of the first conductor film positioned below the nitride film to expose the oxide film in a peripheral area of a formation region of the insulating film; and implanting the P-type impurity from a region from which the oxide film is exposed toward an inside of the semiconductor substrate with a second acceleration energy smaller than the first acceleration energy.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: February 6, 2024
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Tetsuya Yamamoto
  • Patent number: 11894235
    Abstract: A semiconductor manufacturing device including a polishing head that is capable of retaining a semiconductor substrate; a polishing pad having a processing surface to be abutted to the semiconductor substrate retained by the polishing head, the processing surface including a groove; a platen that is capable of rotating about a rotary shaft running along a direction intersecting the processing surface, in a state in which the polishing pad is retained by the platen; a measuring section that outputs a measurement value indicating a height of the processing surface at a predetermined location along a circumference of a circle centered about the rotary shaft of the platen; and a derivation section that derives a depth of the groove from the measurement value of the measuring section.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: February 6, 2024
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventors: Kiyohiko Toshikawa, Hiroyuki Baba
  • Patent number: 11876055
    Abstract: A semiconductor device, including: a semiconductor substrate formed of silicon carbide, components being formed at one surface of the semiconductor substrate; a periphery portion disposed at a pre-specified region of a periphery of the semiconductor substrate, the components not being formed at the periphery portion; and a plurality of trenches or portions of trenches formed at the periphery portion, an interior of each of the trenches being filled with a material with a different coefficient of thermal expansion from the silicon carbide.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: January 16, 2024
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Kenichi Furuta, Masao Tsujimoto, Nobuhiro Terada, Masahiro Haraguchi, Tsuyoshi Inoue, Yuuichi Kaneko, Hiroki Kuroki, Takaaki Kodaira
  • Patent number: 11863132
    Abstract: A switched capacitor amplifier circuit includes an operational amplifier, a first capacitor and a second capacitor each having one end connected to a negative input terminal of the operational amplifier, a first switching circuit configured to connect the other end of the first capacitor and a signal source during a first operation, a second switching circuit configured to connect the other end of the second capacitor and the output terminal of the operational amplifier so as to connect the output terminal and the negative input terminal of the operational amplifier through the second capacitor during the second operation, and an impedance converter circuit configured to convert an output impedance of the signal source into a specified impedance, the impedance converter circuit being connected between the first switching circuit and the other end of the first capacitor.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: January 2, 2024
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Koji Yabe
  • Patent number: 11854952
    Abstract: A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: December 26, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Toshihisa Sone, Kazuya Yamada, Akihiro Takei, Yuichi Yoshida, Kengo Takemasa
  • Patent number: 11831281
    Abstract: A semiconductor integrated circuit is capable of electrically connecting to a capacitance variable capacitor whose electrostatic capacitance changes corresponding to an environmental change between a first and a second capacitances and determines whether the electrostatic capacitance of the capacitance variable capacitor has changed to exceed a reference capacitance value.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: November 28, 2023
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Masayuki Otsuka
  • Publication number: 20230378252
    Abstract: A semiconductor device has: a semiconductor substrate; a trench that extends from a first surface of the semiconductor substrate towards an interior of the semiconductor substrate, and that has a recess/protrusion structure on a side wall surface thereof; a semiconductor film that is formed so as to cover the side wall surface of the trench, be continuous with the side wall surface, and extend onto the first surface of the semiconductor substrate; an opposite electrode having a first portion that is provided at a position opposing the semiconductor substrate while sandwiching the semiconductor film therebetween, and that extends on the first surface of the semiconductor substrate, and a second portion that is continuous with the first portion and extends so as to fill the trench; and an insulating film that insulates the semiconductor film from the opposite electrode.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroshi SHIBATA
  • Patent number: 11804425
    Abstract: An electronic device including: a semiconductor device including plural terminals input with voltages having a same potential; and a wiring board including a mounting region at which the semiconductor device is mounted, wherein the wiring board includes a board wiring line formed on the wiring board from a connection portion at which one terminal of the plural terminals is connected, via an inside of the mounting region, to a connection portion at which another terminal of the plural terminals is connected.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: October 31, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Koya Shimazaki
  • Patent number: 11798509
    Abstract: A display driver drives a display device including a plurality of data lines and a demultiplexer. The demultiplexer includes a plurality of first switches connected to the respective plurality of data lines, and a series of driving voltages including a plurality of driving voltages is supplied via a first wiring. The demultiplexer supplies the plurality of driving voltages to the respective plurality of data lines via the plurality of first switches. The display driver includes: a voltage multiplexing part that generates the series of driving voltages; a second switch connected between the voltage multiplexing part and the first wiring; and a controller connected to the plurality of first switches and the second switch.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: October 24, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroyoshi Ichikura
  • Patent number: 11798905
    Abstract: The semiconductor device according to the present invention comprises; a semiconductor element having one surface with a plurality of electrode pads; an electrode structure including a plurality of metal terminals and a sealing resin. The plurality of metal terminals being disposed in a region along a circumference of the one surface. The sealing resin holding the plurality of metal terminals and being disposed on the one surface of the semiconductor element. The electrode structure includes a first surface opposed to the one surface of the semiconductor element, a second surface positioned in an opposite side of the first surface, and a third surface positioned between the first surface and the second surface. Each of the plurality of metal terminals is exposed from the sealing resin in at least a part of the second surface and at least a part of the third surface.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: October 24, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Takashi Shimada
  • Patent number: 11791220
    Abstract: A semiconductor device, including: a first well of a first polarity formed in a semiconductor substrate; a source region and a drain region of a second polarity formed in the first well so as to be separated from each other by a predetermined spacing; an impurity region of the first polarity formed so as to surround the source region and the drain region; a first gate oxide film formed on the semiconductor substrate at a position between the source region and the drain region; a second gate oxide film formed on the first gate oxide film; a gate electrode formed on the second gate oxide film; and an impurity layer of the first polarity formed below the first gate oxide film.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: October 17, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Toru Mori
  • Publication number: 20230323525
    Abstract: Provided is a cover ring assembly that allows suppressing a dust generation source and reducing adhesion of particles on a substrate. A cover ring assembly for a substrate processing apparatus, which exposes a substrate to processing particles in an internal space to process the substrate, includes an annular flat plate and a cover ring having an annular shape. The annular flat plate has an inner peripheral upper surface and an outer peripheral upper surface. The inner peripheral upper surface is in contact with an outer peripheral lower surface terminating at an outer surface of the substrate. The outer peripheral upper surface is around the inner peripheral upper surface. The cover ring has a lower portion surface having an abutting surface in contact with the outer peripheral upper surface of the annular flat plate. A thermal spraying film covering a surface exposed to the processing particles is disposed to the cover ring except for the abutting surface.
    Type: Application
    Filed: March 24, 2023
    Publication date: October 12, 2023
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Masashi TAKAHASHI, Atsushi CHIBA
  • Patent number: 11764294
    Abstract: A semiconductor device including: a first semiconductor layer having a first conductive type; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a second conductive type that is a conductive type different from the first conductive type; an impurity region of the first conductive type formed at a surface of the second semiconductor layer; first electrodes contacting the impurity region, the second semiconductor layer, and the first semiconductor layer via a first insulating film; and second electrodes contacting the first electrodes via a second insulating film, and contacting the first semiconductor layer via a third insulating film, the second electrodes including PN junctions at borders between upper portions that contact the first semiconductor layer via the third insulating film and lower portions that contact the first semiconductor layer via the third insulating film.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 19, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Tomomi Yamanobe, Yoshinobu Takeshita, Kazutaka Kodama, Minako Oritu
  • Patent number: 11756490
    Abstract: A display device which can suppress erroneous display of a display panel is provided. A source driver receives a serial data signal in which a preamble and video data of the display panel are alternately continuous via an interface from a display controller. The source driver controls timing of supply of a gate signal from a gate driver based on the video data included in the serial data signal, and supplies a gradation voltage signal which corresponds to the video data to a plurality of data lines of the display panel. The source driver has a detection portion which detects that the interface is in an unstable state, and a gate reset signal output portion which outputs a gate reset signal for stopping an operation of the gate driver when the unstable state of the interface is detected at the time of the supply of the video data.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: September 12, 2023
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Yukinobu Watanabe
  • Patent number: 11756991
    Abstract: A semiconductor device has: a semiconductor substrate; a trench that extends from a first surface of the semiconductor substrate towards an interior of the semiconductor substrate, and that has a recess/protrusion structure on a side wall surface thereof; a semiconductor film that is formed so as to cover the side wall surface of the trench, be continuous with the side wall surface, and extend onto the first surface of the semiconductor substrate; an opposite electrode having a first portion that is provided at a position opposing the semiconductor substrate while sandwiching the semiconductor film therebetween, and that extends on the first surface of the semiconductor substrate, and a second portion that is continuous with the first portion and extends so as to fill the trench; and an insulating film that insulates the semiconductor film from the opposite electrode.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: September 12, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroshi Shibata