Patents Assigned to Lapis Semiconductor Co., Ltd.
  • Publication number: 20210104204
    Abstract: A first latch retrieves a pixel data piece for each one horizontal scanning period of a video data signal and holds the pixel data piece as a first pixel data piece. A second latch retrieves the first pixel data piece from the first latch at a timing when the retrieval by the first latch is completed and holds the first pixel data piece as a second pixel data piece. An interpolation data generating unit obtains the first pixel data piece and the second pixel data piece and generates an interpolation data piece. A third latch alternately performs a retrieval of the second pixel data piece and a retrieval of the interpolation data piece, and sequentially outputs the retrieved data piece as a third pixel data piece. A gradation voltage output unit outputs the gradation voltage signal based on the third pixel data piece.
    Type: Application
    Filed: October 6, 2020
    Publication date: April 8, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hideki MASAI
  • Patent number: 10971469
    Abstract: Reliability of joining between semiconductor chips is improved by promoting filling of a sealing resin into a gap formed between the semiconductor chips. A semiconductor device includes: a first semiconductor chip, which has a plurality of first electrodes on a surface; a second semiconductor chip, which is disposed to be separated by a gap from the surface of the first semiconductor chip, and which includes an inner peripheral area that has a plurality of second electrodes connected to each of the first electrodes on a surface and an outer peripheral area that surrounds the inner peripheral area and has a thickness thinner than the thickness of the inner peripheral area; and a sealing resin, which is respectively filled between the surface of the first semiconductor chip and the inner peripheral area, and between the surface of the first semiconductor chip and the outer peripheral area.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: April 6, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Kohei Kurogi
  • Patent number: 10971237
    Abstract: A semiconductor device has stored therein a plurality of bits of fixed data. The semiconductor device includes a plurality of memory elements that correspond, respectively, to the plurality of bits of the fixed data, and that acquire, store, and output the value of each bit received at an input terminal of each of the memory elements according to a timing signal. An initialization control unit feeds, to the plurality of memory elements, an initialization signal upon receipt of a fixed data setting signal, each of the plurality of memory elements being initialized to a state of storing a corresponding value represented by a bit of the fixed data according to the initialization signal.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: April 6, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Takashi Yamada
  • Publication number: 20210098297
    Abstract: There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.
    Type: Application
    Filed: December 10, 2020
    Publication date: April 1, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Osamu KOIKE, Yutaka KADOGAWA
  • Patent number: 10964287
    Abstract: The display apparatus includes: N differential amplifiers having output ends, amplifying N input voltages and outputting amplified voltages, and a resistor ladder having N voltage supply points connected to the output ends of the N differential amplifiers and M voltage output points outputting M level voltages. The M voltage output points are connected to capacitive loads on input sides of the amplifiers, and at least one N differential amplifier has an input pair and an output end connected to one of the N voltage supply point. One of the N input voltages is received by one of the input pair, the other one of the input pair is connected to one of the M voltage output points outputting a level voltage closest to a voltage at the one voltage supply point. The one voltage supply point and the one voltage output point are at different positions on the resistor ladder.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 30, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi Tsuchi, Manabu Nishimizu
  • Patent number: 10963212
    Abstract: A sound source playback unit plays back sound data from a sound source and outputs a playback signal. An amplification unit amplifies the playback signal and outputs the playback signal as an output signal converted to sound in a speaker. A fault detection unit including a first conversion circuit compares the playback signal to a predetermined first threshold, converts a waveform of the playback signal, and outputs the converted waveform as a converted playback signal. A second conversion circuit compares the output signal to a predetermined second threshold, converts a waveform of the output signal, and outputs the converted waveform as a converted output signal. A comparison circuit compares the converted playback signal to the converted output signal, and a determination circuit determines an output of the comparison circuit. Based on the determination, the fault detection unit detects a fault in the amplification unit.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 30, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroji Akahori
  • Patent number: 10964780
    Abstract: The semiconductor device includes a semiconductor substrate of first conductivity type including a cell area and a peripheral area surrounding cell area on a principal surface thereof, a first diffusion layer which is disposed in peripheral area, surrounds the cell area and has a second conductivity type different from the first conductivity type, an electrode which is disposed in the peripheral area, is in contact with the principal surface through an opening provided in an insulating member and is connected to the first diffusion layer, and a second diffusion layer of the first conductivity type which is formed on the principal surface of a region enclosed in the electrode distant from the first diffusion layer when viewed in a direction perpendicular to the principal surface and includes a linear portion having a first width and a curved portion having a portion with a second width greater than the first width.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: March 30, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Kenichi Furuta, Toshifumi Kobe, Toshiyuki Orita, Tsuyoshi Inoue, Tomoko Yonekura, Masahiro Haraguchi, Yoshinobu Takeshita, Kiyofumi Kondo
  • Patent number: 10962621
    Abstract: A communication circuit, a communication system, and a self-diagnosis method of the communication circuit, which facilitate specifying a failed part which causes a communication failure when a communication failure occurs in a communication system, are provided. A serial signal for self-diagnosis is supplied to a first conversion unit, a pulse signal for self-diagnosis corresponding to the serial signal for self-diagnosis output from the first conversion unit is input to a second conversion unit instead of a pulse signal received by a pulse signal reception unit, and the serial signal corresponding to the pulse signal for self-diagnosis output from the second conversion unit is transmitted to the outside via a serial signal transmission unit.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: March 30, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hidekazu Kikuchi
  • Publication number: 20210090519
    Abstract: The display apparatus includes: N differential amplifiers having output ends, amplifying N input voltages and outputting amplified voltages, and a resistor ladder having N voltage supply points connected to the output ends of the N differential amplifiers and M voltage output points outputting M level voltages. The M voltage output points are connected to capacitive loads on input sides of the amplifiers, and at least one N differential amplifier has an input pair and an output end connected to one of the N voltage supply point. One of the N input voltages is received by one of the input pair, the other one of the input pair is connected to one of the M voltage output points outputting a level voltage closest to a voltage at the one voltage supply point. The one voltage supply point and the one voltage output point are at different positions on the resistor ladder.
    Type: Application
    Filed: September 17, 2020
    Publication date: March 25, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi Tsuchi, Manabu Nishimizu
  • Publication number: 20210092298
    Abstract: An imaging device and a horizontal direction detection method capable of detecting a horizontal angle of a camera with high accuracy in a simple configuration are provided. The imaging device includes an imaging unit configured to obtain image data by photographing a predetermined subject, an image rotation unit configured to cause a display image based on the image data to be rotated on a display plane step by step, a count unit configured to count the number of pixels of a specific color included in the display image in a scanning line direction within the display plane and obtain a count value for each of rotated display images, and a determination unit configured to determine a horizontal direction of a photographing angle of the imaging unit based on the count value for each of the rotated display images.
    Type: Application
    Filed: December 9, 2020
    Publication date: March 25, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Yuki Imatoh
  • Patent number: 10958215
    Abstract: A semiconductor device includes a resistor element connected to one and another end of a crystal oscillator, and an adjustable current type inverter element having an input connected to one end of the resistor element and an output connected to another end of the resistor element. A first capacitor element is connected to the input of the inverter element and to ground, and a second capacitor element has one end connected to ground. A first switching element switches a connection state of the one end of the first capacitor element and another end of the second capacitor element. A third capacitor element is connected to the output of the inverter element and to ground, and a fourth capacitor element has one end connected to ground. A second switching element switches a connection state of the one end of the third capacitor element and another end of the fourth capacitor element.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 23, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Tetsuo Oomori
  • Patent number: 10958267
    Abstract: A power-on clear circuit includes a first inverter unit including a constant current transmission unit having one end supplied with a first power supply voltage, and a first transistor having a first terminal connected to a second line kept at a fixed potential, a second terminal connected to the other end of the constant current transmission unit, and a control terminal receiving application of a second power supply voltage which varies to follow the first power supply voltage; a second inverter unit that operates on the basis of the first power supply voltage, and to which a potential of a first node is input, the first node is connected between the other end of the constant current transmission unit and the first terminal of the first transistor; and a signal outputting unit that outputs a power-on clear signal in accordance with an output of the second inverter unit.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: March 23, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Seiichiro Sasaki
  • Patent number: 10957638
    Abstract: A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: March 23, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Osamu Koike
  • Publication number: 20210074198
    Abstract: The present invention includes: a first decoder that outputs mutually different two voltages as first and second selection voltages based on a first bit group of a digital data signal in a first selection state, and outputs one or both of the two voltages as the first and the second selection voltages in a second selection state; a second decoder that outputs mutually different two voltages as third and fourth selection voltages based on a second bit group of the digital data signal in the first selection state and outputs one voltage based on the second bit group as the third and the fourth selection voltages in the second selection state; and an amplifier circuit that averages a combination of the first and the second selection voltages or the third and the fourth selection voltages with predetermined weighting ratios and outputs the averaged voltage.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 11, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroshi TSUCHI
  • Publication number: 20210065639
    Abstract: A display driver according to the present invention includes a control part and a fault detection circuit. The control part sequentially incorporates first fault detection data and second fault detection data into a video signal during non-display periods of the video signal. The fault detection circuit binarizes each of a first pixel driving voltage and a second pixel driving voltage with a predetermined threshold voltage to obtain a first signal and a second signal. The first pixel driving voltage is generated based on the first fault detection data. The second pixel driving voltage is generated based on the second fault detection data. The fault detection circuit determines whether the first signal and the second signal match and outputs a fault detection signal that indicates a presence of a fault when the first signal and the second signal match.
    Type: Application
    Filed: August 19, 2020
    Publication date: March 4, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroaki ISHII
  • Patent number: 10930638
    Abstract: The disclosure provides a semiconductor device that can reduce the area of the circuit elements formed thereon. The semiconductor device includes a first conductivity type region formed on a substrate and formed with a resistance element surrounded by an insulating film; a second conductivity type region laminated in contact with an upper surface of the resistance element; a capacitor formed on the resistance element via an interlayer insulating layer; a via electrically connecting a terminal of the resistance element and a terminal of the capacitor in series; and a power supply line and a ground line electrically connected to the other terminal of the resistance element and the other terminal of the capacitor respectively.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: February 23, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Chikashi Fuchigami
  • Patent number: 10930981
    Abstract: A semiconductor device includes: a boosting section configured to output a second voltage boosted from a first voltage; a voltage lowering section configured to output a lowered voltage that has been lowered from the second voltage by a predetermined voltage; a first buffer amp including a non-inverting input terminal connected to an output of the voltage lowering section; a second buffer amp including a non-inverting input terminal that is input with the first voltage; and a difference output section configured to output a voltage corresponding to a difference between output of the first buffer amp and output of the second buffer amp.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: February 23, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Naoaki Sugimura
  • Patent number: 10923173
    Abstract: A voltage generating circuit, a semiconductor memory device, and a voltage generating method are provided. The voltage generating circuit includes: an oscillation signal generating part generating an oscillation signal that alternately repeats a state of a first voltage and a state of a second voltage; a capacitor having one end receiving the oscillation signal and an other end connected to an output node; a switch element receiving a control voltage and set to an on state or an off state according to the control voltage, and applying the first voltage to the output node when set to the on state; and a switch control part supplying, as the control voltage to the switch element, the second voltage when the oscillation signal is in the state of the first voltage, and a voltage of the output node when the oscillation signal is in the state of the second voltage.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: February 16, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Akira Akahori
  • Publication number: 20210035548
    Abstract: There is provided a semiconductor device having a timing generator that generates synchronization signals so as to match input timings of serial audio data input from an external source, a reproduction processor that, based on the synchronization signals, reads audio data from memory, performs reproduction processing, and outputs a plurality of channel information items, and a mixer that mixes the plurality of channel information items with the serial audio data, and reproduces an audio signal.
    Type: Application
    Filed: July 23, 2020
    Publication date: February 4, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Atsuhiro KAI
  • Publication number: 20210035520
    Abstract: Display apparatuses, data drivers and display controller are provided. The data drivers receive video signals, generate positive-polarity and negative-polarity gradation data signals with respect to a predetermined reference voltage based on the video signals, output the positive-polarity gradation data signals to one of a first and a second data line groups, and output the negative-polarity gradation data signals to the other data line group. The data drivers generate, as the positive-polarity gradation data signals, signals in which data pulses each having a positive-polarity analog voltage value corresponding to a luminance level of each pixel based on the video signal appear in predetermined cycles, and generate, as the negative-polarity gradation data signals, signals where data pulses each having a negative-polarity analog voltage value corresponding to a luminance level of each pixel appear in each predetermined cycle with phases different from the positive-polarity gradation data signals.
    Type: Application
    Filed: July 26, 2020
    Publication date: February 4, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi TSUCHI, Keigo OTANI