Abstract: A delay cell for use within a voltage controlled oscillator capable of operating at two different selectable frequencies, the delay cell having a first delay stage including a first differential pair of transistors, wherein the emitter or each transistor is coupled to a first common node and further wherein a first current exiting the first common node is selectively variable. The delay cell further having a second delay stage including a second differential pair of transistors, each having an emitter coupled to a second common node wherein a second current exiting the second common node is selectively variable and wherein a sum of the first current and the second current is substantially constant. The amount of delay associated with the first delay stage is dependent upon the level of the first current.
Abstract: The present invention is a CML to CMOS converter which includes a bipolar input stage, a current source/current sink stage, and an output stage. The converter is able to transfer a CML input voltage differential to a CMOS compatible voltage having constant high and low voltage levels with a constant duty cycle. The bipolar input stage receives an incoming CML voltage differential and steps the voltage levels down. Utilizing the stepped down CML voltage differential, the current/source sink drives the output stage by maintaining an equal current source and current sink to and from the output stage, ensuring that an output voltage at the output stage rises and falls to constant high and low voltage levels, thereby maintaining a constant duty cycle. A first pair of NMOS transistors, coupled to the output stage drive current to the output stage from a high input voltage rail whenever the input differential is high.
Abstract: A circuit and a method for comparing an input voltage to an internally generated reference voltage utilize a bias network to make the voltage comparison. The bias network is preferably configured to generate a proportional-to-absolute-temperature (PTAT) reference voltage, which is used for the voltage comparison. Although the circuit can be implemented to operate in a number of applications, the circuit is particularly useful in a current sensing application. The circuit includes the bias network, a comparison current path and an output terminal. The comparison current path is configured to partially duplicate a current path of the bias network on which the reference voltage is generated. The comparison current path includes a current control element and an active transistor. Depending on the input voltage applied to the active transistor of the comparison current path, the output terminal is driven to generate either a high or a low comparison signal.
Abstract: A modular power supply which distributes responsibility for supplying current to a load among two or more power supply modules having a common output node. One of the power supply modules which supplies the lowest level of current to the load functions as the master while the remaining power supply modules each function as a slave. A load share bus which interconnects all the power supply modules is driven by the master with a signal representative of the level of current supplied by the master. Each slave module attempts to reduce its output current to a level which is a predetermined offset above the level of current supplied by the master while a regulated voltage is maintained at the common output node. Any one of the modules can become the master, though once the system is operating, the predetermined offset generally prevents the roles from changing. Should one of the power supply modules fail such that its output current is uncontrolled, this power supply module will not be the master.
Abstract: A two-stage differential to single-ended amplifier. The input stage converts a differential voltage to a differential current. A first pair of bipolar input transistors are biased with constant currents. Therefore, their on-resistance does not affect gain linearity. Changes in input voltages induce currents in a first pair of field effect transistors (FETs) each having a gate coupled to the collector of a corresponding input transistor and a drain coupled to the emitter of the corresponding input transistor. Differential currents are provided to the output stage by a second pair of FETs, each configured to mirror the current in a corresponding one of the first pair of FETs. Gain is adjustable by enabling additional pairs of FETs configured as current mirrors. The output stage includes a second pair of bipolar transistors with bases coupled together and biased with equal currents. Currents from the input stage are applied to the emitters of the second pair of bipolar transistors.
October 2, 1998
Date of Patent:
August 22, 2000
Micro Linear Corporation
Robert Zucker, Carlos A. Laber, David Ritter
Abstract: A method and apparatus for interleaving switching of multiple transistor switches in a power factor correction (PFC) boost converter and for timing the switching to occur when a current through a freewheeling diode corresponding to each switch is at a minimum level. The converter draws input current from an alternating current power supply for forming a regulated output voltage. A controller senses an input current and an output voltage across an output capacitor for controlling switching to regulate the output voltage and to ensure that the input current is substantially in phase with an input voltage. Current through a first inductor associated with a first switch is allowed to fall substantially to zero upon discharging the first inductor prior to re-charging the first inductor. Charging of a second inductor associated with a second switch, however, is initiated prior to completion of discharging the first inductor.
Abstract: The present invention provides two or more output voltages from one input voltage and one inductor. Each output voltage is formed by a switch controlling the charge delivered to each of the corresponding output capacitors. Preferably, a diode is placed in series with each switch that controls the charging of the output capacitors to prevent any extraneous stray current from escaping while the switch is closed. The controller utilizes pulse width modulation to deliver the correct amount of energy to each load and to synchronize the order of energy delivery to each load. The use of one input voltage and one inductor for charging multiple output voltages simplifies the complexity of the circuit of the present invention and eliminates the need for a single inductor dedicated to each load. Further, the predetermined output voltage level for each load can be changed without modifying the passive elements in the circuit.
Abstract: A low dropout (LDO) voltage regulator for generating a well-regulated voltage which is stable with variations in load resistance and in supply voltage includes a non-complex reference voltage generator. In the preferred embodiment, the reference voltage generator is configured to function as an amplifier as well as a reference voltage generator. In one embodiment, a single gain stage LDO voltage regulator utilizes the single function reference voltage generator which is compared to a feedback voltage that is proportional to an output voltage. The feedback voltage and the reference voltage control two currents which are used to generate a control signal to a pass transistor. Depending on the supply voltage, the pass transistor either increases or decreases the current to an output terminal to raise or lower the output voltage until the output voltage equals the regulated voltage. In another embodiment, a two gain stage LDO voltage regulator utilizes the dual function reference voltage generator.
Abstract: A temperature monitoring circuit with thermal hysteresis in CMOS circuitry utilizes bipolar transistors which are parasitic to standard CMOS circuitry. A concept of band-gap circuitry is used to provide a proportional to absolute temperature (PTAT) current, which is used as a reference. An output signal is produced above a predetermined temperature by comparing current changes between the PTAT current and a PTAT controlled current in a single current path. The PTAT controlled current decreases faster with temperature increase than the change in the PTAT current. The thermal hysteresis is accomplished by inverting the output signal to control a hysteresis transistor for selectively shorting out a hysteresis resistor. In the preferred embodiment, a start circuit is attached to the temperature monitoring circuit with thermal hysteresis to provide an initial current to activate the present invention. The start circuit is quickly shorted out once the devices of the present invention are turned on.
Abstract: A circuit that senses a current signal in a secondary winding of a transformer by monitoring a current signal in a primary winding of the transformer. The monitored current signal contains an effective current component and a magnetization current component. The magnitude of the effective current signal is related to the magnitude of the current signal in the secondary winding by the turns ratio of the transformer. The magnetization current signal produces flux in the transformer core and does not contribute to producing current in the secondary winding of the transformer. In addition, the magnetization current is 90 degrees out of phase with the effective current signal in the primary winding. The effective current signal in the primary winding is in phase with the voltage signal applied to the primary winding. The invention integrates the monitored current signal over 0 degrees to 180 degrees of the effective current signal waveform.
Abstract: A battery power conversion circuit comprising a cell equalization circuit that ensures that each cell in a multiple battery cell stack is depleted of charge at an equal rate. The stack is coupled to provide current to a primary winding of a transformer. Each of the nodes between cells is coupled to the primary winding of the transformer through a transistor such that an equal number of turns of the primary winding are present between each node. An additional transistor coupled in series with the primary winding controls the current through the primary winding such that a capacitor coupled to a secondary winding of the transformer may be charged by an induced secondary current to a desired voltage level for powering a load. A controller circuit monitors the output voltage level and controls the transistor in series with the primary winding for maintaining the desired load voltage through a feedback loop.
Abstract: A circuit and method for providing a voltage regulation despite variations in the supply voltage and/or the load utilize a MOS synchronous rectifier in a flyback topology to perform both step-up and step-down operations. The circuit operates in a boost-type operation until the voltage at an output terminal exceeds a predetermined shut-off voltage. At such time, a duty cycle of the circuit is suspended until the voltage at the output terminal falls below the predetermined shut-off voltage. Triggering the duty cycle and the suspension of the duty cycle are dependent solely upon the voltage at the output terminal. The circuit includes a steering device that connects the body of MOS synchronous rectifier to either its source or its drain to consistently configure the MOS synchronous rectifier in a reverse-biased condition. Preferably, the steering device is comprised of two PMOS transistors that are controlled by the voltages at the source and drain of MOS synchronous rectifier.
Abstract: A two-stage switching regulator having low power modes responsive to load power consumption. A first stage of the regulator is a power factor correction (PFC) stage. A second stage is a pulse-width modulating (PWM) stage. When a load draws a high level of current, switching in both stages is enabled. Under certain conditions, switching in either one or both of the stages is disabled by the duty cycle for the corresponding switch falling to zero. When switching in both stages is enabled, as in a normal mode, switching in the PWM stage is then disabled in response to an error signal falling below a first error threshold. When switching in the PFC stage is enabled and switching in the PWM stage is disabled, as in a first low power mode, switching in the PFC stage is then disabled in response to a feedback voltage rising above a first feedback threshold.
Abstract: A circuit that forms a square wave pulse train signal wherein each pulse is centered about a zero crossing of a reference sinusoid. A first capacitor is coupled to be charged and discharged at equal rates by a first transconductance amplifier. Upon a first positive zero crossing of the reference sinusoid, the first transconductance amplifier begins charging the first capacitor. Upon the first negative zero crossing, the first transconductance amplifier begins discharging the first capacitor until a first predetermined voltage level is reached. Upon reaching the first predetermined voltage level, the first transconductance amplifier begins charging the first capacitor again. The voltage on the first capacitor is compared by a first comparator to a second predetermined voltage level higher than the first voltage level. The output of the first comparator is a pulse which is centered about a second positive zero voltage crossing of the reference sinusoid.
Abstract: A controlled output voltage is provided for a switching mode power converter operating in the continuous conduction mode without requiring a feedback path coupled to monitor the output voltage. Instead, a voltage related to the input voltage is monitored. The monitored voltage is compared to a periodic waveform for forming a switch control signal. In the case of a buck converter operating as a voltage regulator, over each period of the periodic waveform, the periodic waveform is representative of the inverse function. In the case of a boost converter operating as a voltage regulator or buck converter operating as a bus terminator or power amplifier, over each period of the periodic waveform, the periodic waveform has a linear slope. The switch control signal controls a duty cycle of the power switches. Therefore, switching is controlled in an open loop, rather than in a closed loop.
Abstract: A voltage regulator and method of voltage regulation utilizes an error amplifier and a transconductance amplifier together with a voltage reference, startup circuit and output load. The use of the transconductance amplifier allows the use of an arrangement of two poles and a zero such that the composite gain roll-off has a generally constant slope. One of the poles utilized in this stability scheme is the outer pole formed by the resistive-like load and its filter capacitor. Another pole and zero are generated in the error amplifier circuit. To decouple the noisy input supply voltage, sensitive parts of the circuit are powered by the regulated output voltage. A start circuit is provided to start up the output and voltage reference when no output voltage is present. The transconductance amplifier block has special characteristics which allow it to work to relatively high frequency, above the gain bandwidth product of the control loop. It is driven by a fully differential push-pull, class AB amplifier.
Abstract: A current sense circuit utilizes multiple resistive reference switches connected in electrical series to reduce the level of required reference current (Iref), while maintaining the integrity of tracking current (Iout) through a resistive power switch. Typically, all of the reference switches are MOS transistors connected in electrical series. The first embodiment includes establishing a ratio (n) of series reference transistors to series pilot transistors, n>1. In another embodiment, the series connection of reference switches is in parallel with a single reference resistor and is identical to a series connection of a number (NP) of pilot switches. In a third embodiment, the techniques of the first two embodiments are combined (i.e., n>1 and NP>1). The current sense circuit is utilized to monitor output current through a power switch from a circuit load.
Abstract: A controller for a switched reluctance motor that does not utilize a sensor for detecting the rotational position of the rotor. The inductance of each field winding changes according to the rotational position of the rotor. The rotational position of the rotor of the motor is determined by measuring the inductance of each phase during periods when a minimum level of inductance for the phase is expected to occur. A series of voltage pulses are applied to the appropriate field winding during the appropriate period while the current produced in response to the voltage pulses is measured. The relationship between applied voltage, measured current, and time, is utilized to determine the inductance value as it decreases and then increases between positions of rotor alignment. Commutation to a next phase is performed based upon the measured inductance values.
Abstract: An adaptive equalizer is configured to reconstruct electronic signals which are transmitted over signal cables, such as twisted pair cables. The equalizer satisfactorily reconstructs the signals over a broad range of cable lengths. Using the known degradation characteristics for a cable over a desired range of lengths, the adaptive equalizer includes multiple equalization paths, each of which are configured to reconstruct the input voltage signal optimized for a particular cable length. The degraded input signal is split according to a predetermined relationship into an appropriate two of the multiple equalization paths as controlled by a control logic circuit. Though each path is optimized to reconstruct the signal for a particular length of cable, the adaptive control adds a function of the actual cable length for more accurately reconstructing the signal. Each of the two active paths forms a partially reconstructed signal which is summed to form a composite reconstructed output signal.
Abstract: A transmission termination circuit able to reduce transmission signal reflections and resultant data corruption such that a single network may selectively communicate data using either a voltage driven transceiver or a current driven transceiver. A 10BASE-T transceiver has differential voltage driven outputs. A first output is coupled to a first terminal of a primary winding of a transformer through a first resistor. A second output is coupled to a second terminal of the first primary winding through a second resistor. A 100BASE-TX transceiver has differential current driven outputs. A first output is coupled to a first terminal of a second primary winding of the transformer. A second output is coupled to a second terminal of the second primary winding. A resistive snubber comprising a resistor in series with a capacitor is coupled across the 100BASE-TX outputs. A twisted-pair network is coupled to a secondary winding of the transformer.