Abstract: An adaptive equalizer is configured to reconstruct electronic signals which are transmitted over signal cables, such as twisted pair cables. The equalizer satisfactorily reconstructs the signals over a broad range of cable lengths. The degradation characteristics of a signal cable varies with cable length. Using the degradation characteristics for a cable over a desired range of lengths, the adaptive equalizer includes multiple parallel paths each of which are configured to reconstruct the input voltage signal optimized for a particular cable length. The degraded input signal is split according to a predetermined relationship into multiple partial signals, each signal for transmission through one each of the paths. Though each path is optimized to reconstruct the signal for a particular length of cable, the adaptive control adds a function of the actual cable length for more accurately reconstructing the signal. Each path forms a partial reconstructed signal.

Abstract: A micropower switching regulator for use in a hysteretic current-mode switching mode power converter monitors a fraction of the voltage output to the load in order to maintain the output voltage at a desired level. When the output voltage is less than the desired level, a proportional current is generated, representative of the difference between the output voltage and the desired level, and used to control the switching regulator causing an inductor to alternate between charging to a hysteretic maximum current level and then discharging to a hysteretic minimum current level, controlled by the switching regulator, until the output voltage is greater than the desired level. The hysteretic maximum and minimum current levels vary as the proportional current varies, so that as the difference between the output voltage and the desired voltage increases or decreases, the current level in the inductor will also increase or decrease, responsively.

Abstract: A circuit for forming a substantially periodic signal having a linear relationship between amplitude and time over a portion of its period, wherein a slope in the linear portion is controllable. A transconductance amplifier has a gain which is controllable depending upon a level of biasing current. A capacitor is coupled to an output of the transconductance amplifier wherein a voltage level on the capacitor defines the periodic waveform. Logic signals coupled to inputs to the transconductance amplifier control a direction of current flow from the transconductance amplifier to charge and discharge the capacitor. The biasing current is controllable to control a slope of the periodic waveform. In the preferred embodiment, the invention is used in conjunction with a circuit for forming pulses centered about positive zero crossings of a sinusoidal signal. The biasing current to the transconductance amplifier has two components.

Abstract: A circuit that utilizes a Zener diode to protect elements of a circuit from an over-voltage condition. When a fault occurs, causing an over-voltage condition, the voltage applied to the elements of the circuit is limited by the Zener diode. In addition, the circuit senses the over-voltage condition. Upon sensing the over-voltage condition, the circuit gradually reduces the power applied to that portion of the circuit to a minimum level. If the over-voltage condition persists for a predetermined amount of time, power is shut down to that portion of the circuit until the circuit is re-started. Because the amount of time that an over-voltage condition may occur is limited, the Zener diode may have a lower power rating than would otherwise be required. This is because the power dissipation capabilities of a Zener diode conducting current under a reverse bias are greater when the reverse bias is of a short duration than when the reverse bias is of a long duration.

Abstract: A circuit for providing a regulated output voltage from a buck converter without directly monitoring the output voltage. The buck converter includes a switch having a first terminal coupled to a supply voltage and a second terminal coupled to a first terminal of an inductor and to a first terminal of a resistive divider. A second terminal of the inductor is coupled to a first capacitor for forming the output voltage across the first capacitor. A voltage formed by the resistive divider is applied to an inverting input of a transconductance amplifier, while a reference voltage is applied to a non-inverting input of the transconductance amplifier. An output of the transconductance amplifier is coupled to a second capacitor for forming an error signal across the second capacitor. The error signal is representative of a difference between the output voltage and a desired output voltage because an average of the voltage formed by the resistive divider is representative of the output voltage.

Abstract: A circuit for synchronizing a periodic ramp signal utilized in a switching mode power converter to system clock signal. A capacitor is charged through a resistor. When a voltage across the capacitor reaches a predetermined level, the capacitor is discharged and the charging cycle is repeated, thereby generating the periodic ramp signal across the capacitor. A waveform shaping circuit shapes the ramp signal into a rectangular wave signal having a same frequency and phase as the ramp signal. A phase comparator compares a phase of the rectangular wave signal to a phase of the system clock signal for forming a phase error signal. The phase error signal controls a level of current supplied to the timing capacitor by a voltage controlled current source. When the frequency of the system clock signal is higher than the frequency of the ramp signal, the phase comparator causes the voltage controlled current source to supply additional current to the capacitor, increasing the frequency of the ramp signal.

Abstract: A DC-to-DC converter having hysteretic inductor current limiting and that does not have a resistor continuously carrying the inductor current. A voltage supply is coupled to a drain of a first transistor. A source of the first transistor is coupled to a first terminal of the inductor and to a drain of a second transistor. A source of the second transistor is coupled to ground through a resistor. A second terminal of the inductor is coupled to a first terminal of a capacitor. When the first transistor is on, the second transistor is off, causing current in the inductor to increase. The current flowing through the inductor charges the capacitor, and stores energy in the inductor as an increasing magnetic field. When the first transistor is off, the second transistor is on, and the stored energy is converted back into current, continuing to charge the capacitor. Voltage across the capacitor is regulated for powering a load by controlling the first and second transistors in a feedback loop.

Abstract: A nonlinear carrier controlled power factor correction circuit operates in the continuous and discontinuous conduction modes and provides unity power factor at the input of a power supply by only sensing the output voltage and the current flowing through a diode of a rectifier circuit. The power factor correction circuit monitors a level of current flowing through the diode and generates an integrated voltage signal representative of the level of current flowing through the diode. The integrated voltage signal is compared to a periodic, carrier waveform signal generated using a feedback signal corresponding to a level of an output voltage delivered to a load. A difference between the feedback signal and a reference signal determines the waveshape and characteristics of the carrier waveform. Preferably, leading edge modulation is used to control the duty cycle of a switch within the rectifier circuit.

Abstract: A combination PFC-PWM integrated circuit converter controller having a power factor correction stage and a pulse-width modulation stage. The power factor correction stage provides unity power factor and a regulated intermediate output voltage by sensing a current in the power factor correction circuit and by sensing the regulated intermediate output voltage in a voltage control loop. The regulated intermediate output voltage is sensed by an error amplifier that includes a current mirror. A dc supply voltage for powering the integrated circuit is generated that is representative of the regulated intermediate output voltage. The dc supply voltage is sensed for an overvoltage protection function. By sensing the intermediate regulated output voltage in the voltage control loop and by sensing the dc supply voltage for overvoltage protection, a component failure is less likely to affect both functions than if a single voltage was sensed for both functions.

Abstract: A circuit for driving a brushless dc motor includes an active deceleration circuit for rapidly slowing the motor. A phase locked loop senses a position of the rotor for commutating from a drive state to a next drive state in a sequence of drive states at an appropriate time for maintaining torque on the rotor in the direction of rotation. Thus, the rotor "chases" the energized windings. A speed control loop controls current in the windings and, thus, motor speed. When the speed of the motor exceeds a desired speed by more than a threshold amount, rather than commutating to a next drive state in the sequence, the circuit skips a commutation. By skipping one commutation, the current drive state is maintained while the rotor continues to turn, due to its own inertia, such that the rotor "passes up" the current drive state. This results in a torque on the rotor in a direction opposite rotation.

Abstract: An operational amplifier having an input and an output stage. The input stage includes first and second source-coupled NMOS input transistors for accepting a differential input voltage and first and second PMOS load transistors for supplying current to each input transistor. A node between the first input transistor and first load transistor is coupled to a gate of a third PMOS transistor having its source coupled to a positive supply and its drain coupled to the sources of the input transistors and to a negative supply through a first biasing transistor. The output stage includes a fourth PMOS transistor having its gate coupled to a node between the second input transistor and the second load transistor and a source coupled to the positive supply voltage. A drain of the output transistor forms an output node and is coupled to the negative supply through a second biasing transistor.

Abstract: A circuit for powering a two-phase AC induction motor. The circuit generates a first signal of the form Vdc+A sin(2.pi.ft-0.degree.) and a second signal of the form Vdc+A sin(2.pi.ft-90.degree.). The first signal is input to a first error amplifier along with a first sampled difference signal from the motor. The second signal is input to a second error amplifier along with a second sampled difference signal from the motor. The outputs from each of the first and second amplifiers is input into a first comparator and a second comparator along with a sawtooth waveform to create a first sinusoidally modulated square wave signal and a second sinusoidally modulated square wave signal. The first and second sinusoidally modulated square wave signals are fed to driver circuits which in turn control an H-bridge circuit for powering the motor from a DC bus.

Abstract: A technique for sensing current that employs an internal current sensing resistor. Two current sources of small and equal magnitude pull currents from two identical PNP transistors. Two PMOS transistors supply current to the PNP transistors. The PMOS transistors are scaled so the transistor on the output side of the circuit has an aspect ratio much greater than that of the transistor on the sensing side of the circuit. The result is that the currents through the PMOS transistors are proportional to each other and the current on the sensing side is much smaller than the current on the output side. The output current is the difference between the current through the PMOS transistor with the greater aspect ratio and the current through one of the small current sources. The sensing current, which passes through the internal sensing resistor, is the difference between the current flowing through the PMOS transistor with the lesser aspect ratio and the current flowing through the other small current source.

Abstract: A circuit for sensing a current in a fluorescent lamp. A control system comprises a buck regulator circuit for supplying a buck current, an inverter circuit for receiving the buck current and for generating a lamp voltage, a circuit for sensing a current in a fluorescent lamp, and a controller for controlling the buck regulator and the inverter. The inverter comprises a Royer-type inverter, a resonant tank, and a transformer. A current flows through a primary winding of the transformer to generate a voltage in a secondary winding of the transformer. The fluorescent lamp is coupled to the secondary winding of the transformer so that the fluorescent lamp is isolated from the remainder of the control system by the transformer. The circuit for sensing the current in the lamp senses a current in the Royer-type inverter which is representative of the current in the lamp. The circuit for sensing the current in the lamp is coupled to the controller for controlling the buck regulator and the inverter.

Abstract: A switching mode power converter monitors the level of power supplied to a load device. The operation of a switch is controlled and used to draw power from an input source and supply power to the load device. During normal operation, the operation of the switch is triggered on every clock pulse by a triggering pulse. The duty cycle of the triggering pulse is controlled by a pulse width modulation circuit which monitors the level of power being supplied to the load device. When the power being supplied to the load falls to a predetermined light load threshold level, representing that the load device is either in a standby mode or a period of light use, the switching mode power converter will reduce the amount of power being drawn from the input source by disabling the triggering pulse for an appropriate number of pulses of the clock signal. The number of pulses skipped will depend on an amount of power being supplied to the load device and an amount of voltage stored across the capacitor.

Abstract: An integrated circuit controller for power factor correction circuit that provides unity power factor by sensing only a current in the power factor correction circuit and a dc supply voltage. The power factor correction circuit is coupled to a circuit for generating the dc supply voltage. Thus, the dc supply voltage is representative of the regulated output voltage of the power factor correction circuit. The dc supply voltage is sensed and integrated over each clock cycle and compared to an inverted and amplified version of the sensed current for controlling operation of the power factor correction circuit. By sensing the dc supply voltage, rather than the output voltage of the power factor correction circuit, the integrated circuit requires fewer pins. In a preferred embodiment, the integrated circuit also includes a pulse width modulation controller circuit.

Abstract: A degenerated differential pair waveform builder has a single ramp generator control circuit and a plurality of differential pairs. A trigger input is generated and input to the ramp generator control circuit. The ramp generator control circuit then generates a differential signal which is output to each of the differential pairs through a positive edge signal node and a negative edge signal node. Each differential pair then generates an output in response to the differential signal output from the ramp generator control circuit. The outputs from the differential pairs are combined in a summing circuit which outputs a composite waveform. Each differential pair has an associated ramp time which is dependent upon the value of the resistance in its emitter circuit. The ramp time of each differential pair directly affects the slope of its resulting output waveform.

Abstract: A signal generator generates a reference signal, centered about a reference voltage and having a predetermined period. The signal generator also generates output signals P and Z. The output signal P is a squarewave which changes levels at the peaks of the reference signal. The output signal Z is a squarewave which changes levels at the reference voltage crossings of the reference signal. A phase-shifted signal generator generates a phase-shifted signal using the output signals P and Z by switching in appropriate signal levels from the signal generator. The output signals P and Z are input to a switch control circuit which controls a network of switches, depending on a current region of the reference signal, to couple appropriate signals to an amplifier circuit. The switch control circuit determines the current region based on the state of the output signals P and Z. The amplifier circuit provides the phase-shifted signal in response to the signals coupled to it by the network of switches.

Abstract: A circuit for powering a three-phase AC induction motor. The circuit generates a first signal of the form Vdc+A sin (2.pi.ft-0.degree.) and a second signal of the form Vdc+A sin (2.pi.ft-90.degree.) as is done in conventional circuits for powering two-phase AC induction motors. A vector summation circuit is used to create a third signal from the first two signals. The third signal is of the form Vdc+A sin (2.pi.ft+60.degree.). The first signal is input to a first error amplifier along with a first sampled difference signal from the motor. The third signal is input to a second error amplifier along with a second sampled difference signal from the motor. The outputs from each of the first and second amplifiers is input into a first comparator and a second comparator along with a sawtooth waveform to create a first sinusoidally modulated square wave signal and a second sinusoidally modulated square wave signal.

Abstract: A low drop-out regulator circuit that has high ripple rejection and low power consumption. A first local feedback loop is a high-speed, high-bandwidth loop that actively rejects noise from the input source to the regulator. A second feedback loop, having lower speed and a correspondingly lower bandwidth than the first feedback loop, regulates the output voltage. Each feedback loop is separately optimized for its respective bandwidth requirements and, therefore, the regulator is highly efficient. The first feedback loop comprises an amplifier and a pair of PMOS transistors configured as a current mirror with current gain. The first feedback loop generates a first current for charging an output capacitor. Feedback ensures that the first current is proportional to a second current generated by the second feedback loop while rejecting noise from the input source.