Abstract: A multiple output flyback DC-to-DC converter with synchronous rectification and constant on-time current-mode control. A controller includes a constant on-time, minimum off-time oscillator that is coupled to control a gate of a first transistor which controls a current through a primary winding of a transformer having three secondary coupled inductors. Each of the three secondaries is coupled to a capacitor which is charged by each secondary current to an output voltage level which depends, in part, upon a ratio of windings. A transistor is coupled between each secondary winding and a resistive network. The gates of these transistors are coupled to be controlled by the controller for synchronous rectification. The resistive network monitors the secondary currents by generating a voltage signal that is representative of a weighted sum of the inductor currents.
September 19, 1995
Date of Patent:
September 2, 1997
Micro Linear Corporation
Urs Harald Mader, Daryl Jay Sugasawara, Joseph Brian Vanden Wymelenberg
Abstract: A series clock deskewing apparatus uses a series terminated single transmission line system to deliver a clock signal to a load. A plurality of series clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads simultaneously. Each series clock deskewing apparatus has a single series termination resistor with the same impedance value as the transmission line to which it is coupled. For each load, the clock signal travels the transmission line from a clock generator to the load and is simultaneously applied to the deskewing apparatus. A clock signal is reflected at the load back to the deskewing apparatus. The roundtrip transit time is determined by the deskewing apparatus which causes an appropriate delay to adjust each clock signal to arrive synchronously at all the loads.
Abstract: A circuit for supplying power to a fluorescent lamp. A control system comprises a buck regulator for supplying a buck current, an inverter circuit for receiving the buck current and for generating a lamp voltage, a circuit for sensing a current in a fluorescent lamp, a circuit for sensing a no lamp condition, and a controller for controlling the buck regulator and the inverter. The circuit for sensing a no lamp condition monitors a voltage level at the inverter transformer. The controller is coupled to the circuit for sensing a no lamp condition. If a no lamp condition is detected, the controller responds by shutting itself down. The controller can be reactivated by toggling an on/off signal to reset a latch.
Abstract: A clock deskewing apparatus uses either a series terminated single transmission line system or a Thevenin terminated dual transmission line system to deliver a clock signal to a load. A plurality of series terminated clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads coupled to the clock signal simultaneously. Each series clock deskewing apparatus has a single termination resistor with the same impedance value as the transmission line that it is coupled to. Each Thevenin termination system has a voltage divider resistor network. A variable delay line within each series clock deskewing apparatus can be adjusted so that each load receives the clock signal at the same time. A programmable output driver impedance network can be used for the single line termination resistor of the series terminated clock deskewing system in order that the series terminated clock deskewing apparatus can be used with transmission lines having different line impedances.
Abstract: An oscillator for generating a varying amplitude feed forward power factor correction (PFC) modulation ramp signal includes a clock generating circuit and a ramp generating circuit. The PFC ramp signal generated by the ramp generating circuit is used within a power factor correction circuit of a switching mode power converter. The timing capacitor used within the ramp generating circuit is charged from the full wave rectified line input voltage so that the amplitude of the generated ramp output signal will follow the full wave rectified input signal, thereby maintaining the current loop bandwidth at a constant value and improving the transient response of the circuit. A one-shot circuit is coupled between the discharge transistor of the clock generating circuit and the discharge transistor of the ramp generating circuit for synchronizing the clock and ramp reference signals generated by the oscillator so that the frequency of the ramp reference signal is equal to the frequency of the clock signal.
Abstract: A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation, and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. This 20MHz 6th order Bessel filter and 2nd order equalizer operate from 5V, and generate only 0.24% (-52dB) of total harmonic distortion when processing 2Vp-p differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36Mbps, and is built in a 1.5 .mu./4GHz BiCMOS technology.
Abstract: The invention is an active, hot insertable, SCSI terminator circuit having a bypass device that permits an initially unpowered active SCSI terminator to be coupled to a signal line of a powered SCSI bus such that no damage results to the SCSI terminator circuit itself or to other SCSI devices on the SCSI bus, and without having the effect of altering the existing state of the SCSI bus as a result of the coupling. Preferably, the terminating element of the SCSI terminator is a p-channel MOSFET. The SCSI terminator is prevented from being damaged during the coupling by using the bypass device to effectively short the gate of the p-channel MOSFET terminating element to its drain. When the drain of the p-channel MOSFET terminating element is shorted to its gate the amount of current the SCSI terminator may draw from any and all SCSI signal lines during the coupling is substantially limited to less than 50 .mu.A.
Abstract: The present invention is for an active rectifier for use in a DC to DC converter wherein a feedback control circuit activates and de-activates the current conduction between the input and the output. Preferably, the current conductor between the input and the output is a P-type MOSFET, wherein the feedback control circuitry provides the activation or de-activation signal to the gate of this transistor. The feedback control circuitry provides an activation signal to the transistor when the input voltage is greater than the output voltage, and provides a de-activation signal to the transistor when the input voltage is equal to or less than the output voltage. Because the P-MOS rectifier has a lower voltage drop than the Schottky diode, the forward drop is reduced. In addition, the feedback control circuit is designed to draw no current except when the P-MOS rectifier is conducting.
Abstract: The invention employs an active element, a p-channel MOSFET, between a regulated voltage and a SCSI terminating line. An "ideal" current source terminator is most effective when a signal line is negated (low-to-high transition), whereas a resistive terminator is most effective when a signal line is asserted (high-to-low transition). The I-V characteristics of a p-channel MOSFET, wherein the relationship between the termination voltage and the termination current is characterized by a nonlinear and smooth voltage versus current curve, provide an optimized transient response for signal negations and signal assertions on a SCSI bus.
Abstract: A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit uses an active integrator. The integrator has a left-half plane pole. A feedback path is provided that includes a resistive impedance which comprises a MOS transistor operated in the triode region. The resistive impedance is adjustable for cancelling the pole. The feedback path also includes a capacitive impedance coupled in series with the resistive impedance.
Abstract: An R-C relaxation oscillator having two comparators and a silicon controlled rectifier dissipates very low average power without resulting in frequency instabilities due to circuit propagation delays. A timing capacitor C.sub.T is charged through a timing resistor R.sub.T. The first comparator compares the voltage across the timing capacitor with an upper threshold voltage V.sub.TH. When the voltage across the timing capacitor crosses the upper threshold voltage, the comparator turns on the silicon controlled rectifier, which causes the capacitor to discharge the voltage that it has stored. The second comparator turns off the silicon controlled rectifier when the voltage across the timing capacitor falls below a lower threshold voltage V.sub.TL.
Abstract: A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation, and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. This 20MHz 6th order Bessel filter and 2nd order equalizer operate from 5V, and generate only 0.24% (-52 dB) of total harmonic distortion when processing 2 Vp-p differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36 Mbps, and is built in a 1.5.mu./4 GHz BiCMOS technology.
Abstract: An output circuit includes a totem-pole output circuit for driving a power MOSFET. A pull-up circuit and a pull-down circuit drive the output node low or high as required. The circuit prevents the pull-up and pull-down circuits from simultaneously conducting current. The pull-up circuit has a pull-up threshold voltage and the pull-down circuit has a pull-down threshold voltage such that the pull-up circuit is turned off before the pull-down circuit is activated when the output node is switched from a high state to a low state and further wherein the pull-down circuit is turned off before the pull-up circuit is activated when the output node switches from a low state to a high state. The pull-up circuit is held off when the output node is switched from a high state to a low state by two diodes from the output node to an input of the pull-up circuit.
Abstract: A self calibrating algorithmic analog-to-digital converter is disclosed for which the gain of the conversion loop is precisely adjusted and controlled by an array of switched capacitors such control being stored in a latch. The offset of the gain stage is reduced by reducing the amount of charge injected from the gate of the input zeroing MOS switch.
Abstract: The present invention is for an architecture for an input circuit to a linear circuit having a circuit ground from a linear system having a system ground. The architecture has a linear input signal which is coupled into a current limiting input impedance. The current limiting input impedance is not connected to the system ground. A linear input circuit is coupled to receive the reduced input signal and is coupled to the circuit ground. Accordingly, the analog input to the linear input circuit is a current signal rather than a voltage signal.
Abstract: This invention is for a transconductance amplifier. The amplifier has an amplifier input and an amplifier output with an amplifier output impedance. An input stage of the amplifier has a first transconductance. An intermediate state is coupled to the amplifier output through positive feedback. The intermediate stage has a second transconductance and an intermediate stage output having an intermediate output impedance. The gain of the amplifier is a function of the first transconductance times the second transconductance times the amplifier output impedance times the intermediate output impedance.
Abstract: An electrically programmable security system includes a receiver responsive to particular radio frequency signals which include a predetermined digital code encoded on the radio frequency signal. The receiver generates a control signal upon detecting the presence of the encoded radio frequency signal. The receiver also includes a circuit for digitally communicating the predetermined digital code on a communication link. A transmitter includes a memory for storing a digital code and a circuit for generating a radio frequency signal at the radio frequency to which said receiver is responsive. The radio frequency signal generated by the transmitter is encoded with the digital code stored in the memory. The transmitter further includes a circuit for coupling with the communication link and a circuit for inputting the predetermined digital code from the receiver unit communicated on the communication link into the memory when the communication link is coupled to the coupling circuit.
Abstract: An improved miniature hand-held low power transmitter utilizing a surface acoustic wave (SAW) resonator as the control element to establish the carrier frequency of the oscillator. The SAW resonator stabilizes the frequency of the transmitter to within 0.05% of the center frequency of the SAW resonator for the condition of the user's hand enclosing the transmitter. This stability allows the companion receiver to operate at a narrow bandwidth, 0.1% of the center frequency of the SAW resonator, thus reducing the spurious noise received by the receiver. The configuration of the transmitter allows schemes such as pulse position or pulse width modulation to be utilized to encode the transmitted information. The physical size of the SAW resonator allows the transmitter to be mounted within a housing small enough to be enclosed by the user's hand.
Abstract: In a thermal radiation measuring arrangement, a thermal radiation detector is located at the focal point of a collecting mirror, upon which incident thermal radiation from a surface, such as a building wall, is directed. The thermal radiation detector may be, for example, a thermopile, and provides an output signal having a magnitude proportional to the amount of thermal radiation which it receives. The temperature detection means detects the temperature of the thermal radiation detector and, for example, may detect the cold junction of the thermopile. In a first operating condition, a signal summing means receives the output signal from the thermal radiation detector and the temperature detection means and provides a third output signal proportional to the sum of these first and second output signals. In a second operating condition, a signal biasing means is connected into the signal summing means.