Abstract: Switching regulator methods and systems are provided for supplying output current at a regulated voltage level to a load. Upon determining that the output current is not below a predetermined current threshold, the regulator is operated in a continuous mode. The input voltage is monitored. If the input voltage is not below a first input threshold level, the system remains in continuous mode. Otherwise, the system enters a burst mode in which the switch mode power supply is turned OFF, thereby reducing transistor gate charge losses.

Abstract: A current sensing circuit may include a shunt resistance through which current to be sensed travels. A first and a second differential amplifier may each provide an amplified output of the voltage across the shunt resistance. A switching system may deliver a current sensing signal output based on the amplified output of the first differential amplifier when the common mode voltage across the shunt resistance is low and based on the amplified output of the second differential amplifier when the common mode voltage across the shunt resistance is high. The first differential amplifier may provide its lowest output DC offset voltage when the common mode voltage is low, while the second differential amplifier may provide its lowest output DC offset voltage when the common mode voltage is high. The first and second differential amplifiers may both have a low common mode voltage rejection ratio, such as a ratio of less than 40 db at the switching frequency of switches that control the current that is sensed.

Abstract: A DC-coupled differential amplifier has an output common-mode voltage near the ground reference. A feedback circuit superimposed on a trans-linear loop improves linearity and extends the bandwidth of the basic PNP differential pair.

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract: Power Sourcing Equipment (PSE) provides a PoE supply voltage over data wires to a Powered Device (PD). A PSE controller controls a first FET that couples the PoE voltage to the data wire pairs and controls a second FET that couples the data wire pairs to the spare wire pairs. Upon powering up, the PSE controller keeps the two FETs open and performs a detection routine on any devices connected to the data pairs and spare pairs. If a PoE-compatible PD is detected as being coupled to the data pairs, the first switch is closed. If it is determined that the PoE voltage should also be coupled to the spare pairs, the second FET is also closed. The method prevents the PoE voltage from being applied to the spare pairs when the device connected to the spare pairs is not PoE compatible and maintains backwards compliance with IEEE PoE PDs.

Abstract: Sample-and-hold (S/H) circuitry operating in track and hold phases and having a first S/H circuit with a first hold capacitor at which a first voltage value is maintained in the hold phase, and a dielectric absorption (DA)-suppressing circuit connectable to the first hold capacitor for operating the S/H circuitry in an additional phase after completing the hold phase and before entering the track phase. The DA-suppressing circuit is configured to supply the first hold capacitor, during an operation in the additional phase, with a second voltage value that is negatively correlated with the first voltage value.

Abstract: A configurable signal-processing circuit may provide a plurality of selectable signal-processing operations. The configurable signal-processing circuit may have a configuration circuit that provides a configuration code that selects a first signal-processing operation from the plurality of selectable signal-processing operations based on a timing pattern for evaluating an input signal and outputting an output signal.

Abstract: A system for producing an output signal representing movement of an object's surface has a continuous wave (CW) signal source for producing an CW signal directed at the object's surface. The CW signal is produced at a first frequency. A receiving element receives a signal reflected from the object's surface when the CW signal hits this surface. A down-converting frequency mixer converts the received signal into a signal of a second frequency lower than the first frequency. The frequency mixer is configured to produce an output signal representing an amplitude-modulated (AM) component of the received signal and having a parameter representing movement of the object's surface.

Abstract: A circuit may sense the differential voltage across two nodes that each have a non-zero common mode voltage. The circuit may have a positive input impedance that is imposed across the nodes. An impedance compensation circuit may generate a compensation current that is delivered to the nodes that substantially cancels the loading effect of the positive input impedance. The impedance compensation circuit may generate a negative input impedance that is imposed across the two nodes that is substantially the same as the positive input impedance. The impedance compensation circuit may instead be configured to deliver the compensation current to the nodes.

Abstract: An anemometer and method for analyzing fluid flow is described. In one embodiment, a transistor sensor is heated by applying power to cause its base-emitter junction to rise from an ambient first temperature to a second temperature. The power is removed, and the Vbe is measured at intervals as the junction cools. The Vbe equates to a temperature of the junction. The temperature exponentially decreases, and the time constant of the decay corresponds to the fluid flow velocity. A best fit curve analysis is performed on the temperature decay curve, and the time constant of the exponential decay is derived by a data processor. A transfer function correlates the time constant to the fluid flow velocity. The transistor is thermally coupled to a metal rod heat sink extending from the package, and the characteristics of the rod are controlled to adjust the performance of the anemometer.

Abstract: A converter generates an output voltage differential across a floating load, such as a string of LEDs. The converter receives an input voltage Vin from a power supply, and the floating output voltage differential may be greater than or less than Vin. The converter uses a first switch and first inductor in a boost mode type configuration, and uses a second switch and second inductor in a buck mode type configuration. The inductors have a common node. The first inductor has another end coupled to ground, and the other end of the second inductor is coupled to the load. Both inductors charge and discharge together depending on the conductivities of the switches. One end of the load will be approximately zero volts, while the other end will be at a negative voltage VEE. The two inductors smooth input current/voltage ripple and output current/voltage ripple, resulting in low EMI.

Abstract: A bootstrapped switch circuit capable of operating at input signals from far below the negative supply rail to far beyond the positive supply rail may include (a) a switch having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a control terminal; (b) a charge pump coupled to one or more clock signals and isolated from a timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to one or more clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump.

Abstract: An anti-lash nut assembly for installation on a threaded rod and including a lead nut, a collar, and a spring positioned between the lead nut and the collar. The lead nut has a set of tabs extending radially outward from a rear end of the body. The collar has a set of clearance slots on an inside surface. The set of clearance slots are configured for sliding of the set of tabs through the clearance slots in the rear direction. The collar has a set of ramps on an inside surface. Each of the set of ramps is configured for engagement with each of the set of tabs to prohibit axial movement of the collar in the rear direction.

Abstract: A current mode power conversion system and method operates in cycles. Each cycle includes an on time and an off time. The system includes an inductor connected to store energy during the on time of each cycle and use the energy during the off time of each cycle. The system provides a stable output voltage and a maximum-limited output current to a load during constant load conditions. The system comprises a feedback control linearly operable so as to control the output voltage across the load during constant load conditions, and non-linearly operable so as to control the output voltage across the load during certain detected changes in load conditions as a function of the derivative of the current in the inductor so as to speed up the transient response of the power conversion system when a fault condition exists.

Abstract: A linear regulator integrated circuit may be formed having four external terminals including a voltage input (Vin) terminal, a voltage output (Vout) terminal, a Set terminal, and an operational amplifier (op amp) power terminal. A user connects an external resistor to the Set terminal for creating a reference voltage. An op amp controls a pass (or series transistor) to cause an output voltage at the Vout terminal to equal the reference voltage. The op amp has a first power supply terminal internally coupled to the Vin terminal and a second power supply terminal coupled to the op amp power terminal. The op amp power terminal allows a user to externally couple the op amp second power supply terminal to either the Vout pin (for high voltage applications), system ground (for medium voltage applications), or another voltage (to provide additional headroom in very low voltage applications).

Abstract: A sampling circuit may include a sampling capacitance, an electronic sampling switch, and a switch controller. The electronic sampling switch may have a control input that controls whether the electronic sampling switch is in a sample state or a hold state. The electronic sampling switch may connect the sampling capacitance to an input signal while in the sample state and disconnect the sampling capacitance from the input signal while in the hold state. The switch controller may control the control input to the electronic sampling switch so as to cause the electronic sampling switch to be in the sample state during one period and the hold state during another period. While in the sample state, the switch controller may cause the impedance of the electronic sampling switch that is seen by the input signal to be substantially independent of the voltage of the input signal.

Abstract: A power supply system includes a regulator circuit responsive to an input signal at the input node for producing an output signal at the output node at a desired level. The regulator circuit has a controller, an inductive element and a first switch coupled to the inductor element and controlled by the controller to produce the output signal. Also, the power supply system includes a Coulomb counter for producing a Coulomb count signal proportional to the number of Coulombs passing from the input node to the output node. The Coulomb counter is enabled by an enabling signal representing a predetermined time period, for determining the number of Coulombs passing from the input node to the output node during that predetermined time period.

Abstract: A tunable and trimmable analog filter may include a tunable analog filter and a trimming circuit. The tunable analog filter may set the frequency of a characteristic of the tunable analog filter based on a digital tuning signal that is indicative of a desired frequency of the characteristic. However, the tunable analog filter may contain components having values that deviate from specified values due to variations during manufacture of the tunable analog filter. The value deviations can cause the frequency of the characteristic not to precisely match the frequency indicated by the digital tuning signal. The trimming circuit may include a non-volatile memory that contains data. The trimming circuit may receive tuning information indicative of a desired frequency for the characteristic of the tunable analog filter.

Abstract: A system for and method of providing a signal proportional to the absolute temperature of a semiconductor junction is provided. The system comprises: a preprocessing stage configured and arranged so as to process a signal from the semiconductor junction so as to produce a preprocessed signal including a resistance error term; and a temperature to voltage converter stage for converting the preprocessed signal to a voltage proportional to absolute temperature representing the absolute temperature of the semiconductor junction; wherein the system is configured and arranged so as to remove the resistance error term so as to produce a resistance error free signal representative of the semiconductor junction temperature.

Abstract: Circuits and methods for converting a signal from analog to digital. A random number generator provides a random number to a memory. The memory is preconfigured to include codes of predetermined digital to analog (DAC) configurations that provide the maximum amount of DAC gradient suppression. At least one Flash reference generation DAC (FRGD) has an input coupled to the memory unit and an output providing a reference voltage level for its respective Flash comparator. The Flash comparators compare the analog input signal to their respective reference voltage and provide a digital output signal based on the comparison.