Patents Assigned to Linear Technology
  • Publication number: 20140312955
    Abstract: A single-balanced balun mixer circuit includes a balun with a center tap connected to a differential pair with a tail resistor. The balun receives a first input signal and a second signal at the single-ended input terminal and the center tap, respectively. Such a balun mixer may be used as an up-converter mixer by supplying a baseband or intermediate signal at the center tap and a local oscillator (LO) signal at the single-ended input terminal.
    Type: Application
    Filed: October 23, 2013
    Publication date: October 23, 2014
    Applicant: Linear Technology Corporation
    Inventor: Petrus M. STROET
  • Patent number: 8866554
    Abstract: A method of improving the slew rate of an amplifier is described where a differential pair of transistors receives a differential first control signal and second control signal. The tail current for the transistors is provided by a tail current regulator. The same control signals are applied to a slew boost controller, whose output increases as the differential between the control signals increase. The tail current regulator generates a bias signal that sets a minimum tail current. The tail current is controlled to be the minimum tail current until the slew boost output signal exceeds a threshold, whereupon the tail current increases in response to an increasing differential between the control signals. Common mode rejection is not adversely affected by the slew boost controller generating a slightly varying current under common mode conditions due to the minimum tail current.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 21, 2014
    Assignee: Linear Technology Corporation
    Inventor: Thomas Lloyd Botker
  • Patent number: 8866553
    Abstract: A driver for an analog-to-digital converter (ADC) has an overall feedback loop between its input and its output for maintaining overall accuracy, and a much faster feedback loop in its output stage that quickly compensates for output transients before the overall feedback loop can substantially react to the transients. Output voltage transients are created by the intermittent capacitive load of the ADC. The fast feedback loop can be made very fast since there are only a few components in the fast feedback path. The fast reduction of the output transients enables a shorter sampling time, leading to more accurate analog-to-digital conversion. The overall gain of the driver can be set to be greater than unity while still providing good output transient suppression.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 21, 2014
    Assignee: Linear Technology Corporation
    Inventor: Thomas Lloyd Botker
  • Publication number: 20140306662
    Abstract: A monitoring device includes an input terminal configured to receive an input signal from a battery system management (BSM); an output terminal configured to output cell parameters used to determine an open cell voltage associated with one of a plurality of cells within the battery stack connected to the monitoring circuit based on the input signal received from the BSM; a processor; and a memory storing executable instructions for causing the processor to: measure a cell voltage associated with the one of the plurality of cells within the battery stack; measure a voltage drop associated with a measured balancing current; calculate the open cell voltage by adjusting the measured cell voltage based on the measured voltage drop; and balance the battery stack based on the calculated open cell voltage, wherein balancing and calculating the open cell voltage are performed concurrently.
    Type: Application
    Filed: April 4, 2014
    Publication date: October 16, 2014
    Applicant: LINEAR TECHNOLOGY CORPORATION
    Inventors: Dave Daekyum KIM, Robert Jon MILLIKEN
  • Patent number: 8853885
    Abstract: An apparatus and method for load sharing among N current supplies, where N>1. N current supply paths are coupled to corresponding N independent power sources, respectively. A system load is coupled to the outputs of the N current supply paths to receive N current supplies. There is a common current share bus configured to connect to the N current supply paths to provide a common current share signal, used to indicate the current contribution needed from each of the N current supply paths. In this configuration, each of the N current supply paths adjusts an adjustable voltage drop between its power source and the current supply it provides to the system load in accordance with the common current share signal so that the current supplied from each current supply path is consistent with the common current share signal.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: October 7, 2014
    Assignee: Linear Technology Corporation
    Inventors: Christopher Bruce Umminger, David Henry Soo, Mitchell Edward Lee, Pinkesh Sachdev, Zhipeng Li
  • Patent number: 8841962
    Abstract: Methods and systems for a differential correlated double sampling (CDS) switched capacitor integrator circuit. The circuit includes a differential amplifier that has a differential input and a differential output. There is a first feedback path between the negative output node and the positive input node, and a second feedback path between the positive output node and the negative input node. Each feedback path includes an integration capacitor and at least one switch that has a parasitic capacitance. A first capacitive element is coupled between the negative input node and the negative output node, and a second capacitive element is coupled between the positive input node and the positive output node. Each capacitive element is configured to cancel the parasitic capacitance of its corresponding feedback path.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: September 23, 2014
    Assignee: Linear Technology Corporation
    Inventor: Gerd Trampitsch
  • Publication number: 20140266435
    Abstract: A method of improving the slew rate of an amplifier is described where a differential pair of transistors receives a differential first control signal and second control signal. The tail current for the transistors is provided by a tail current regulator. The same control signals are applied to a slew boost controller, whose output increases as the differential between the control signals increase. The tail current regulator generates a bias signal that sets a minimum tail current. The tail current is controlled to be the minimum tail current until the slew boost output signal exceeds a threshold, whereupon the tail current increases in response to an increasing differential between the control signals. Common mode rejection is not adversely affected by the slew boost controller generating a slightly varying current under common mode conditions due to the minimum tail current.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: LINEAR TECHNOLOGY CORPORATION
    Inventor: Thomas Lloyd Botker
  • Publication number: 20140281080
    Abstract: A novel readdressing circuit is provided for supporting data communications over a data line and a clock line between at least one master device and multiple slave devices. For example, the master device and the multiple slave devices may be configured to communicate over an I2C bus including the data line and the clock line. The readdressing circuit has a data input node for receiving a data signal transferred over the data line and including an address word produced by the master device, and a data output node coupled to the multiple slave devices. The readdressing circuit also includes an address generator and an address transmit detections circuit. The address generator is configured for storing a multi-bit fixed offset value. The address generator is responsive to the address word at the data input node for generating multiple unique addresses for the multiple slave devices.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: LINEAR TECHNOLOGY CORPORATION
    Inventor: Daniel James EDDLEMAN
  • Publication number: 20140266393
    Abstract: In a bipolar transistor, a thin gate oxide, preferably less than 600 ?, is formed over the base surface region between the emitter and collector. A conductive gate, such as doped polysilicon, is then formed over the gate oxide and biased at the emitter voltage. In the example of a PNP transistor, when the emitter is forward biased with respect to the base to turn the transistor on, the gate is at a positive potential relative to the base. This causes the holes in the base conducting the emitter-collector current to be repelled away from the surface, and the electrons in the base to be attracted to the surface, so that more of the emitter-collector current flows deeper into the base. Thus, the effect of defects at the base surface is mitigated, and 1/f noise is reduced. The invention is equally applicable to PNP and NPN transistors. Other benefits result.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: LINEAR TECHNOLOGY CORPORATION
    Inventor: Thomas Lloyd Botker
  • Publication number: 20140268909
    Abstract: Switching regulator methods and systems for supplying output current at a regulated voltage level to a load. The regulator has a primary side that is galvanically isolated from a secondary side. The regulator includes a transformer having a primary winding on the primary side and a secondary winding on the secondary side, coupled to a load. A switch, coupled to the primary winding, controls current flow through the primary winding. A first feedback control loop, responsive only to primary side signal values, regulates a constant average voltage at the output node. An optional second feedback control loop, responsive only to primary side signal values, reduces voltage ringing at the output node.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: LINEAR TECHNOLOGY CORPORATION
    Inventors: Thomas Anthony DIGIACOMO, Michael George NEGRETE
  • Publication number: 20140266108
    Abstract: An amplifier circuit has a voltage input terminal, for receiving Vin, and a voltage output terminal, for outputting Vout. A feedback circuit controls Vout to match Vin. A differential input stage receives Vin and Vout and generates a first output signal. An output stage comprises a pull down circuit for Vout. A main MOSFET is controlled by the first output signal to pull down Vout to match Vin when Vout is above a threshold voltage Vtrans. An auxiliary MOSFET, in parallel with the main MOSFET, is controlled by the first output signal to pull down Vout to match Vin when Vout is below Vtrans. The main MOSFET is turned substantially off when Vout is below Vtrans. A headroom generator coupled between the Vout terminal and a drain of the auxiliary MOSFET allows the auxiliary MOSFET to operate in its active region and pull Vout to ground.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: LINEAR TECHNOLOGY CORPORATION
    Inventor: Thomas Lloyd Botker
  • Publication number: 20140266840
    Abstract: A driver for an analog-to-digital converter (ADC) has an overall feedback loop between its input and its output for maintaining overall accuracy, and a much faster feedback loop in its output stage that quickly compensates for output transients before the overall feedback loop can substantially react to the transients. Output voltage transients are created by the intermittent capacitive load of the ADC. The fast feedback loop can be made very fast since there are only a few components in the fast feedback path. The fast reduction of the output transients enables a shorter sampling time, leading to more accurate analog-to-digital conversion. The overall gain of the driver can be set to be greater than unity while still providing good output transient suppression.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: LINEAR TECHNOLOGY CORPORATION
    Inventor: Thomas Lloyd Botker
  • Patent number: 8831211
    Abstract: Circuitry and methodology for providing data transmission in a Power over Ethernet (PoE) system having a Power Sourcing Equipment (PSE) for providing power to a PoE link, and a Powered Device (PD) coupled to the PoE link for receiving the power from the PSE. The PSE and PD support data communication with each other in a common mode between two pairs of lines in an Ethernet twisted pair cable.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: September 9, 2014
    Assignee: Linear Technology Corporation
    Inventors: David McLean Dwelley, John Arthur Stineman, Jr.
  • Patent number: 8823345
    Abstract: This invention uses new switching regulator structures to split single magnetic loops into multiple magnetic loops, with linked opposing magnetic fields, to cause a cancelling effect, resulting in a much lower overall magnetic field. This results in lower EMI. In one embodiment, synchronously switched transistors are divided up into parallel topside transistors and parallel bottomside transistors. The topside transistors are positioned to oppose the bottomside transistors, and bypass capacitors are connected between the pairs to create a plurality of current loops. The components are arranged to form a mirror image of the various current loops so that the resulting magnetic fields are in opposite directions and substantially cancel each other out. Creating opposite current loops may also be achieved by forming the conductors and components in a figure 8 pattern with a cross-over point.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: September 2, 2014
    Assignee: Linear Technology Corporation
    Inventors: Leonard Shtargot, Daniel Cheng, John Gardner, Jeffrey Witt, Christian Kueck
  • Patent number: 8823352
    Abstract: In a current mode controlled switching power supply, current through the inductor is sensed to determine when to turn off or on the switching transistors. The inductor current has a higher frequency AC component and a lower frequency DC component. The AC current feedback path, sensing the ramping ripple current, is separate from the DC current path, sensing the lower frequency average current. Separating the current sensing paths allows the signal to noise ratio of the AC sense signal to be increased and allows the switching noise to be filtered from the DC sense signal. The gain of the DC sense signal is adjusted so that the DC sense signal has the proper proportion to the AC sense signal. The AC sense signal and the DC sense signal are combined by a summing circuit. The composite sense signal is applied to a PWM comparator to control the duty cycle of the switch.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: September 2, 2014
    Assignee: Linear Technology Corporation
    Inventor: Jindong Zhang
  • Publication number: 20140239970
    Abstract: A method for detecting an open-circuit in an external thermocouple network includes these steps: (a) injecting a current pulse of a predetermined duration into the external thermocouple network; and (b) measuring the voltage across the pair of terminals after a time period following the predetermined duration. In one example, the time period is sufficiently long to allow the current pulse to dissipate from the external thermocouple circuit when a thermocouple in the external thermocouple network does not have an open circuit. The thermocouple network may include a resistor-capacitor network provided between the thermocouple and one of the terminals.
    Type: Application
    Filed: January 30, 2014
    Publication date: August 28, 2014
    Applicant: Linear Technology Corporation
    Inventors: Michael Keith Mayes, Todd Stuart Kaplan, David Edward Bliss
  • Publication number: 20140240035
    Abstract: An integrated circuit includes (a) an analog-to-digital converter operated according to a first clock signal; and (b) a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a frequency that is different from a frequency of the first clock signal, such that a noise level introduced by the charge pump into the analog-to-digital converter is less than the average noise level over a predetermined range of frequencies for the second clock signal. The integrated circuit may further include a clock divider circuit (e.g., a programmable clock divider) that generates both the first clock signal and the second clock signal.
    Type: Application
    Filed: January 30, 2014
    Publication date: August 28, 2014
    Applicant: Linear Technology Corporation
    Inventors: Michael Keith Mayes, Todd Stuart Kaplan, David Edward Bliss
  • Publication number: 20140241400
    Abstract: In a temperature sensing circuit, a method for measuring a resistance of a RTD device to sense temperature includes (a) connecting a first terminal of the RTD device to a first current source and connecting a second terminal of the RTD device to a second current source; (b) measuring a first voltage across the RTD device; (c) connecting the second terminal of the RTD device to the first current source and connecting the first terminal of the RTD device to the second current source; (d) measuring a second voltage across the RTD device; and (e) deriving the resistance of the RTD device based on the first voltage measurement and the second voltage measurement. The RTD device may be connected in series with a sense resistor to ground.
    Type: Application
    Filed: January 30, 2014
    Publication date: August 28, 2014
    Applicant: Linear Technology Corporation
    Inventors: Michael Keith Mayes, Todd Stuart Kaplan, David Edward Bliss
  • Patent number: 8819472
    Abstract: Apparatus and method for clock edge synchronization among a plurality of devices. One of the plurality of devices is designated as a master device and one or more remaining devices as slave devices. The master device is configured for providing one or more gated master output clock signals based on a synchronization input signal and an input clock signal. The master device may be further configured to generate one or more gated master clock outputs to drive one or more slave devices, or to provide one or more slave synchronous master clock outputs. The one or more slave devices are configured for producing one or more slave output clock signals, based on the synchronization input signal and corresponding one or more gated master output clock signals. The one or more slave output clock signals are clock edge synchronized.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: August 26, 2014
    Assignee: Linear Technology Corporation
    Inventors: Leslie Catherine Muscha, Doug Allen LaPorte
  • Publication number: 20140233288
    Abstract: An RMS-DC converter includes a chopper-stabilized square cell that eliminates offset, thus enabling high-bandwidth operation. The chopper-stabilized offset requires only a small portion of the circuitry (i.e., a single component square cell) which operates at high frequencies, and is amenable to using high-bandwidth component square cells. Using the chopping technique minimizes required device sizes without compromising an acceptable square cell dynamic range, thereby maximizing the square cell bandwidth. The RMS-DC converter consumes less power than conventional RMS-to-DC converters that requires a high-frequency variable gain amplifier.
    Type: Application
    Filed: November 27, 2013
    Publication date: August 21, 2014
    Applicant: Linear Technology Corporation
    Inventor: Michael Hendrikus Laurentius KOUWENHOVEN