Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract: Technique for controlling a circuit that converts an AC input voltage into a DC output voltage using transistors arranged in first and second transistor pairs. Each transistor of the first pair is controlled in accordance with polarity of the AC input voltage. Each transistor of the second pair is controlled based on a difference between the AC input voltage and the DC output voltage.

Abstract: Novel circuitry and methodology are provided for correcting the offset associated with a voltage-controlled current source. An offset correction circuit is coupled to the current source to prevent the output current produced by the current source from deviating from a desired level. The current source may include a transconductance amplifier or a chopper amplifier, and may be configured to produce a zero or non-zero value of the output current.

Abstract: A monolithic voltage reference circuit may include a voltage-mode band-gap reference circuit, a temperature independent differential current source, and a temperature dependent differential current source. The voltage-mode band-gap reference circuit may include an error amplifier having differential input nodes. The temperature independent differential current source may be configured to add in or subtract from the differential input nodes a substantially temperature independent differential current with an allocation between the nodes that is controlled by a selectable output voltage trim setting. The temperature dependent differential current source may be configured to add in or subtract from the differential input nodes a substantially temperature dependent differential current with an allocation between the nodes that is controlled by a selectable temperature drift trim setting.

Abstract: Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch.

Abstract: A method for automatically compensating a voltage regulator initially disconnects the error amplifier and compensation network from the feedback loop. A DC bias voltage is applied to the feedback loop to cause the regulator's output voltage to be at 90% of its nominal value. An AC perturbation signal is then added to the DC bias voltage to cause the output voltage to have a ripple at a frequency of the AC signal. The gain of the feedback loop and the phase difference between the AC signal and the ripple is then measured. The measured values are then used to automatically adjust operating characteristics of the error amplifier and the compensation network such that, when these components are connected back in the feedback loop during normal operation, the feedback loop has the desired gain and phase margin at the frequency of the AC signal, such as the loop's unity gain frequency.

Abstract: A switching regulator is configured to provide a regulated voltage to a load while maintaining a substantially maximum output current limit, the switching regulator having a loop gain. In accordance with one aspect the switching regulator comprises: a circuit for adjusting the maximum output current limit in response to a programmable signal independently of the loop gain. In accordance with another aspect, the switching regulator comprises: a resistance sensing element for providing the current output of the regulator, and having a resistance which varies with temperature; and a circuit for maintaining the output current limit at a level independent of the temperature of the sensing element. In addition, in accordance with one aspect, a method of providing a regulated voltage to a load is disclosed in which a substantially maximum output current limit of a switching regulator is maintained.

Abstract: A current sense resistor circuit may include a primary current sense resistor that drifts with age. A secondary current sense resistor may drift with age in substantial unison with the primary current sense resistor. A calibration resistor may not drift with age in substantial unison with the primary current sense resistor. A compensation circuit may compensate for aging drift in the resistance of the primary current sense resistor based on a comparison of the calibration resistor with the secondary current sense resistor. The secondary current sense resistor may be in parallel with the primary current sense resistor, except when the compensation circuit is comparing the calibration resistor with the secondary current sense resistor.

Abstract: A power supply system includes a regulator circuit responsive to an input signal at the input node for producing an output signal at the output node at a desired level. The regulator circuit has a controller, an inductive element and a first switch coupled to the inductor element and controlled by the controller to produce the output signal. Also, the power supply system includes a Coulomb counter for producing a Coulomb count signal proportional to the number of Coulombs passing from the input node to the output node. The Coulomb counter is enabled by an enabling signal representing a predetermined time period, for determining the number of Coulombs passing from the input node to the output node during that predetermined time period.

Abstract: Method and system for measuring the resistance of a resistive structure having at least three nodes. A first calibration signal is determined by measuring a voltage at an output of the resistance structure when no calibration current is injected into a third node between the first and second nodes of the structure. A calibration current is then injected into the third node and a second calibration signal is determined. The absolute value of the difference between the first calibration signal and the second calibration signal is determined, the absolute value being proportional to a product of the resistance of the resistive structure and the calibration current.

Abstract: A battery balancing method and system which includes a plurality of cells connected in series, a balancer for each cell, a monitor configured to determine a state of charge (SOC) of each cell, and a microprocessor. The microprocessor iteratively calculates a SOC error for each cell, based on a theoretical balancing of the Min Q cell and the Max Q cell, until the SOC error is less than or equal to a first threshold; and iteratively re-calculates SOC error based on a net charge or discharge time for each balancer until the SOC error is less than or equal to a second threshold; and when the SOC error is less than or equal to the second threshold, instructs each balancer to physically balance each respective cell based on the respective calculated net charge or discharge time when the second threshold is met.

Abstract: A power converting system is responsive to an input signal to produce an output signal regulated with respect to the input signal. The power converting system has an input node for receiving the input signal, an output node for producing the output signal, and first and second inductive elements. The first inductive element has a first node coupled to the input node, the second inductive element has a first node coupled to the output node. A first switching element is coupled to a second node of the first inductive element. A first capacitive element is coupled between the second node of the first inductive element and a second node of the second inductive element. A control circuit is provided for controlling the first switching element.

Abstract: An automatic voltage compensation circuit in a voltage regulator compensates the output voltage for a voltage drop along lines leading to a remote load. A load capacitor is connected across the load for providing a low impedance across the load during a test phase of the regulator. In one embodiment, during the test phase, the load current is changed up or down a small percentage (e.g., 10%). As a result, the regulator voltage changes due only to the line resistance since the load is bypassed by the load capacitor. The voltage drop at full load current is then derived by detecting the change in regulator output voltage (a fractional voltage drop) and multiplying it. The normal mode is resumed, and the derived voltage drop is added to the regulator output by either compensating the feedback loop or by adding the voltage drop to the output of the regulator.

Abstract: A method of fabricating an instrumentation amplifier to have an improved common mode rejection ratio (CMRR) vs. frequency initially trims resistors in the input amplifiers of the instrumentation amplifier during a DC test, where the inputs are shorted and a DC voltage is applied, so that the output of the amplifier is approximately zero. This will normally cause the transconductances of the two input amplifiers to be different. Thus, the AC CMRR will degrade with frequency. Trimmable capacitors are provided in the input section and are trimmed during a common mode AC test to cause the output voltage to be minimized during the AC test. This causes the two input amplifiers to have the same bandwidth and gm/C ratio.

Abstract: A switching regulator circuit incorporates an offset circuit, connected in a control loop of the regulator circuit, that, in response to a signal indicating an imminent load current step, adjusts a duty cycle of a power switch for the current step prior to the regulator circuit responding to a change in output voltage due to the current step. In one embodiment, a load controller issues a digital signal shortly before a load current step. The digital signal is decoded and converted to an analog offset signal in a feedback control loop of the regulator to immediately adjust a duty cycle of the switch irrespective of the output voltage level. By proper timing of the offset, output voltage ripple is greatly reduced. The current offset may also be used to rapidly change the output voltage in response to an external signal requesting a voltage step.

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract: Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch.

Abstract: A system for combining power to a load in a Powered Device (PD) using Power Over Ethernet (PoE) receives power from a first channel and power from a second channel, via four pairs of wires. A MOSFET bridge for each channel is initially disabled. A bridge controller IC simultaneously senses all the voltages and controls the bridge MOSFETs. The bridge controller IC also contains a first PoE handshaking circuit. A second PoE handshaking circuit is external to the bridge controller IC and operates independently. The body diodes in the MOSFET bridge initially couple the first channel to the second PoE handshaking circuit while isolating the second channel. The second handshaking circuit then couples the first channel to the load. The first handshaking circuit then carries out a PoE handshaking routine for the second channel. Ultimately, the bridge controller controls the bridge MOSFETs to couple both channels to the load.