Abstract: In a Power over Data Lines (PoDL) system that conducts differential data and DC power over the same wire pair, various DC coupling techniques are described that improve DC voltage coupling while attenuating AC common mode noise. Pairs of differential mode chokes (DMCs) are used to share current supplied by a single phase or multi-phase power supply. In one embodiment, one DMC is coupled to the line side of a common mode choke (CMC), and one DMC is coupled to the PHY side of the CMC. The line-side DMC has windings that are loosely magnetically coupled so that DMC does not present a very low impedance to AC common mode noise on the wires. Therefore, the performance of the wires' RC termination circuitry is not adversely affected by the line-side DMC when minimizing reflections of common mode signals.

Abstract: In a PoDL system, a PHY has its I/O terminals coupled to a wire pair via a galvanic isolation transformer and a CMC. Thus, DC power and common mode noise are blocked from the PHY inputs. One end of the secondary winding of the transformer is directly coupled to one winding of the CMC. A DC power supply has its positive voltage terminal directly coupled to the other end of the secondary winding and has its other output terminal (e.g., ground) directly coupled to the other winding of the CMC. An AC-coupling capacitor is coupled between the two outputs of the power supply. Differential signals are applied across the secondary winding to couple the differential signals to the PHY, while the secondary winding conducts the DC voltage to one of the wires (via the CMC), and the ground is coupled to the other one of the wires (via the CMC).

Abstract: A first circuit board includes a master device and slave devices communicating with each other via a local first I2C bus. To allow I2C networks to communicate with each other over long distances, such as up to 1200 meters, a first interface device converts the I2C data signals to encoded differential data over a twisted wire pair. A second interface device on a remote circuit board converts the differential data to data and clock signals on its local second I2C bus coupled to other slave devices on the same board. This is equivalent to the two boards sharing the same I2C bus. The interface devices pull down the serial clock line (SCL) in their local I2C bus while waiting for data, such as an acknowledge bit. The master device generates the clock signal for its local I2C bus, and the remote interface device generates the clock signal for its local I2C bus.

Abstract: A flipchip may include: a silicon die having a circuit side with solder bumps and a non-circuit side; a leadframe attached to the solder bumps on the circuit side of the silicon die; a heat spreader attached to the non-circuit side of the silicon die; and encapsulation material encapsulating the silicon die, a portion of the leadframe, and all but one exterior surface of the heat spreader. The leadframe may have NiPdAu plating on the portion that is not encapsulated by the encapsulation material and no plating on the portion that is attached to the solder bumps.

Abstract: In a system and method for correcting a stress-impaired signal in a circuit, a calibration circuit produces a first calibrated voltage based on a base-emitter voltage of one or more pnp transistors, a second calibrated voltage based on a base-emitter voltage of one or more npn transistors, and a voltage proportional to absolute temperature. A set of reference values are generated based on these voltages. A gain correction factor is calculated based on a function of the set of reference values and a set of temperature-dependent values, and the stress-impaired signal is corrected based on the gain correction factor.

Abstract: One or more Power Sourcing Equipment (PSE) are coupled to points in a network of interconnected nodes. Each node has a first port and a second port. Assume the first port of a first node is receiving DC power from the PSE. The first node, at its second port, then detects an electrical signature from a first port of an adjacent second node. If the proper electrical signature is presented by the adjacent second node, the powered first node closes a switch to pass power between its first port and second port to power the second node via the first port of the second node. All nodes in the network are then sequentially powered up in this manner. If there is a fault between the first node and the second node, the second node will be powered by another node connected to the second port of the second node.

Abstract: A hybrid power converter includes a primary switching circuit, an LC circuit, and a secondary switching circuit. The primary switching circuit includes three or more switching transistors in series that may turn on or off according to a switching cycle to generate a series of voltage pulses at a connecting node between two switching transistors. The LC circuit may be coupled via the to the secondary switching circuits to the connecting node of the primary switching circuit. The LC circuit may receive, from the primary switching circuit, a series of pulses via the secondary switching circuits and may generate an inductor current in the LC circuit. The inductor current may charge a capacitor of the LC circuit to generate an output voltage of the hybrid power converter. The output voltage may have a reverse polarity with respect to an input voltage that may be coupled to the primary switching circuit.

Abstract: Various examples described herein are directed to a differential controller including a first regulator and a second regulator. The first regulator receives a first regulator control signal and generates a first regulator output signal. The second regulator receives a second regulator control signal and generates a second regulator output signal. A load is electrically coupled between a first regulator output and a second regulator output. The load current and voltage are based on a difference between the first regulator output and the second regulator output. A current sensor generates a load current signal that describes a load current at the load. A first amplifier generates the first regulator control using the load current signal and a control signal. A second amplifier generates the second regulator control signal using the first regulator input voltage and a common mode voltage.

Abstract: A current mode switching regulator circuit and operating method includes a variable duty cycle power switch controller, a voltage feedback loop that provides a feedback signal based on the output voltage, a current feedback loop that provides a current sense signal based on the output current, and an offset circuit having an external signal input and coupled to the current feedback loop. The power switch controller controls the switching regulator circuit to generate an output voltage and an output current. The offset circuit is configured to provide an offset output control signal, independently of the voltage feedback loop, to control the power switch controller so as to vary a duty cycle of the power switch controller based on the current sense signal and an external offset signal applied to the external signal input.

Abstract: The stability of a channel in a wireless network is evaluated at a node. Upon transmitting a packet from the node on a network channel, a first counter associated with the channel is incremented. Upon receiving an acknowledgment packet responsive to the transmitted packet, a second counter associated with the channel is incremented. A stability metric for the channel is computed based on values stored in the first and second counters. Additionally, interference on a channel of the network is measured at a node. Upon determining that no packet is received during a predetermined time-period on the channel, a received signal strength (RSS) is measured on the channel at an end of the predetermined time-period. Alternatively, upon determining that a packet is received during the predetermined time-period on the channel, the RSS is measured on the channel following completion of the transmission of the packet on the channel.

Abstract: Methods and systems of synchronizing events using a plurality of sequencing controllers are provided. For each sequencing controller, a serial communication bus (SCB) is monitored for a first reference level. Upon identifying that the SCB is at the first reference level for a predetermined period, a bit sequence indicative of an event position is broadcast to be arbitrated on the SCB. The SCB is monitored for the arbitrated bit sequence. Upon determining that the arbitrated bit sequence corresponds to the bit sequence of the event position, an event corresponding to the event position is enabled.

Abstract: A power interface system for reducing power variations includes multiple control circuits configured to control a plurality of switching regulators operating at different frequencies to provide a shared output power to a load. Each control circuit receives a power variation signal resulting from a power variation in the shared output power of the plurality of switching regulators, separates a respective frequency component from multiple frequency components of the power variation signal, and controls, based on the separated respective frequency component, a respective switching regulator of the plurality of switching regulators to source current to, or sink current from, the shared output power until the shared output power reaches a threshold level.

Abstract: The subject technology provides for removing a source of delay in a phase-locked loop (PLL) by causing the output rising edge to occur at the same time as the input rising edge. The subject technology replicates the amount of delay experienced along an input reference signal path to the PLL as close as possible using a same circuit configuration and bias circuits as in the input reference signal path. For example, a timing alignment circuit containing a replica circuit adds compensation delay to a negative feedback loop signal to match the feedback loop delay with the reference path delay. The delay of the reference signal path is estimated and added into the replica circuit. The delay characteristics of these two paths negate one another such that the phases of the input reference signal and the feedback loop signal become phase-locked at the input to the PLL.

Abstract: A stacked package configuration is described that includes a bottom package and an upper package. The bottom package includes a substrate having a top surface with first circuitry and metal first pads. A molded layer is then formed over the substrate. Holes through the molded layer are then laser drilled to expose the first pads. The holes and first pads align with leads of an upper package, which contains further circuit components. The holes are then partially filled with a solder paste. A thermal epoxy is applied between the molded layer and the upper package. The leads of the upper package are then inserted into the holes, and the solder paste is reflowed to electrically, thermally, and mechanically connect the upper package to the bottom package. The reflow heat also cures the epoxy. A ball grid array is then formed on the bottom of the substrate.

Abstract: A network manager of a wireless mesh network is configured to selectively enable or disable communication services provided between devices over the network. The selective enabling or disabling of services may be based on the monitoring and enforcement of license terms set according to license information embedded within the wireless network node(s) or access point(s) of the network. In operation, the network manager retrieves the license information from the node(s) and/or access point(s) of the network, and establishes license terms based on the retrieved license information. In turn, the network manager selectively enables or disables network services, such as by throttling communications relayed between the user application and the nodes, or between nodes, if the license terms are not respected.

Abstract: Methods and systems of pre-balancing a switched capacitor converter are provided. A first comparator includes a positive input configured to receive a voltage across an output capacitor and a negative input configured to receive a first hysteresis voltage. A second comparator includes a positive input configured to receive a voltage across an input capacitor of the switched capacitor converter and a negative input configured to receive a second hysteresis voltage. A first current source is coupled between the output capacitor and GND and is configured to discharge the output capacitor upon determining that the voltage across the output capacitor is above a tolerance provided by the first hysteresis voltage. A second current source is coupled between the input capacitor and GND and is configured to discharge the input capacitor upon determining that the voltage across the input capacitor is above a tolerance provided by the second hysteresis voltage.

Abstract: Techniques to provide automatic-gain ranging for high dynamic range by including a separate S/H capacitor, segmenting the S/H capacitor into a plurality of capacitors, and determining the number of segments to use for a sample. In this manner, the size of the S/H capacitor can be changed (by adjusting the number of capacitors), which can change the amount of input voltage that produces an amount of charge. Using these techniques, the full-scale input range for a sample of the analog input signal can be adjusted automatically based on the magnitude of the sample, which can provide better resolution and/or better noise performance for that particular sample then would otherwise be possible.

Abstract: A method and system of driving a switched capacitor converter having a plurality of switches. A first driver coupled to a first switch is powered by providing a first reference voltage level VCC to a first supply and a GND reference to a second supply node of the first driver. A second driver coupled to a second switch is powered by providing a unidirectional path between the first supply node of a first driver and the first supply node of the second driver and by keeping OFF the second switch while turning ON the first switch. A third driver coupled to a third switch is powered by providing a unidirectional path between the first supply node of a second driver and the first supply node of the third driver and by keeping OFF the first and third switch while turning ON the second switch.

Abstract: In a communications system that conducts differential data via a pair of wires, AC common mode noise is undesirably coupled to the wires in a noisy environment. A hybrid common mode choke (HCMC) attenuates the AC common mode noise while passing the differential data to a PHY. The HCMC includes a CMC (windings with the same polarity) and a differential mode choke (windings with opposite polarities). The CMC attenuates the AC common mode noise, and the DMC passes the attenuated AC common mode noise to termination circuity to eliminate it. Also disclosed is a technique for Kelvin sensing the DC voltage at the pair of wires, in a PoDL system, by detecting the voltage on wires that do not carry DC current, so as to provide a more accurate measurement.

Abstract: A PHY is coupled across a primary winding of an isolation transformer for differential data transmission and reception between PHYs and for DC isolation. Positive and negative low impedance terminals of a DC power supply are coupled to first and second secondary windings of the transformer as split center taps of the transformer. Respective ends of the wires in the wire pair are coupled to the other ends of the secondary windings. Therefore, the power supply conducts DC current through the secondary windings, while the differential data signals also flow through the secondary windings, generating corresponding differential data signals at the inputs to the PHY. The transformer also attenuates common mode noise. Therefore, the circuit makes multi-use of the isolation transformer, allowing fewer components to be used for the DC coupling, wire termination, and common mode noise cancellation.