Abstract: A novel system is offered for supplying power from an input node to a load coupled to an output node. The system may have multiple switches coupled between the input node and the output node. One or more limiting circuits may be configured for controlling the switches so as to limit outputs of the switches. For example, the limiting circuits may limit current through the respective switches. One or more timers may set a delay period for indicating a fault condition after the limiting is initiated.

Abstract: Various techniques are described to terminate a differential wire pair using combinations of CMCs, transformers, autotransformers, differential mode chokes (DMCs), and AC-coupling capacitors. The techniques improve the AC common mode insertion loss without attenuating the differential data signals, while easing the requirements of the CMC. In one example, an autotransformer, having a first winding, a second winding, and a center tap, is connected across a PHY, where the center tap provides a low impedance to ground for attenuating common mode noise. A CMC is coupled across the autotransformer and a pair of wires carrying differential data, where the CMC greatly attenuates common mode noise. The requirements of the CMC are reduced due to the autotransformer.

Abstract: The subject disclosure includes reducing switching losses at lower load current while maintaining the switching frequency for a hybrid switched capacitor converter circuit. Control circuitry is coupled to the hybrid switched capacitor converter circuit and configured to measure a load current at an output of the hybrid switched capacitor converter circuit in a buck phase mode. The control circuitry is configured to compare the measured load current to set of predetermined thresholds. The control circuitry is configured to drive a first voltage to the second set of transistors that turns on the second set of transistors periodically to regulate the output during the buck phase mode. The control circuitry is also configured to drive a second voltage to the first set of transistors that turns off the first set of transistors for one or more switching cycles while the second set of transistors are turned on based on the comparison.

Abstract: In a communications system that conducts differential data via a pair of wires, AC common mode noise is undesirably coupled to the wires in a noisy environment. A hybrid common mode choke (HCMC) attenuates the AC common mode noise while passing the differential data to a PHY. The HCMC includes a CMC (windings with the same polarity) and a differential mode choke (windings with opposite polarities). The CMC attenuates the AC common mode noise, and the DMC passes the attenuated AC common mode noise to termination circuitry to eliminate it. Also disclosed is a technique for Kelvin sensing the DC voltage at the pair of wires, in a PoDL system, by detecting the voltage on wires that do not carry DC current, so as to provide a more accurate measurement.

Abstract: A PHY is coupled across a primary winding of an isolation transformer for differential data transmission and reception between PHYs and for DC isolation. Positive and negative low impedance terminals of a DC power supply are coupled to first and second secondary windings of the transformer as split center taps of the transformer. Respective ends of the wires in the wire pair are coupled to the other ends of the secondary windings. Therefore, the power supply conducts DC current through the secondary windings, while the differential data signals also flow through the secondary windings, generating corresponding differential data signals at the inputs to the PHY. The transformer also attenuates common mode noise. Therefore, the circuit makes multi-use of the isolation transformer, allowing fewer components to be used for the DC coupling, wire termination, and common mode noise cancellation.

Abstract: A technique to eliminate perceptible flickering by LEDs being dimmed by PWM pulses is disclosed. A controllable oscillator controls a switching frequency of a converter for supplying a regulated current or regulated voltage. The converter controls a first switch at a switching frequency. A varying second signal level is generated by a spread spectrum control (SSC) circuit for controlling the oscillator to vary the switching frequency during operation. A PWM dimming circuit generates a string of PWM pulses that control a switch in series with the LEDs. The SSC circuit is synchronized with the PWM pulses to generate the same second signal level at a start of each PWM pulse, such that the switching frequency of the converter is forced to be substantially the same at the start of each PWM pulse while the pulse widths are constant. The repeating driving current waveform eliminates perceptible flicker by the LEDs.

Abstract: A buffer system may have an output for driving a switched load that changes during periods indicated by a switching signal. The buffer system may operate in a closed loop when the switching signal indicates that a load change is not taking place by comparing a signal indicative of the output of the buffer system with a reference voltage. The buffer system may operate in an open loop when the switching signal indicates that a load change is taking place by not comparing signal indicative of the output of the buffer system with the reference voltage. Both the buffer system and the switched load may be on the same chip.

Abstract: A supply circuit comprises a regulated positive supply circuit and an unregulated negative supply circuit. The regulated positive supply circuit includes an inductor arranged to receive input energy from an input circuit node, a switch circuit coupled to the inductor at a switch circuit node, and a control circuit coupled to the switch circuit. The control circuit is configured to control activation of the switch circuit to regulate a voltage at a regulated circuit node and generate a positive output voltage at a positive output circuit node. The unregulated negative supply circuit is operatively coupled to the switch circuit node and is configured to generate a negative supply voltage at a negative output circuit node.

Abstract: A switched capacitor converter includes a primary switching circuit, a flying capacitor circuit, and a secondary switching circuit. The primary switching circuit includes plurality of switching transistors in series. The flying capacitor circuit includes one or more flying capacitors with each flying capacitor connected to a switching transistor. The secondary switching circuit includes two or more switching transistors and provides a first path for charging and a second path for discharging the flying capacitors. At startup, the flying capacitors are discharged via a first current source while the switching transistors are turned off. After discharging, the flying capacitors are charged via a second current source, while a first switching transistor of the primary switching circuit is kept turned off and the rest of the switching transistors perform switching according to a switching cycle. After charging, the switched capacitor converter may enter a steady state operation.

Abstract: An ideal diode circuit is described which uses an NMOS transistor as a low-loss ideal diode. The control circuit for the transistor is referenced to the anode voltage and not to ground, so the control circuitry may be low voltage circuitry, even if the input voltage is very high, referenced to earth ground. A capacitor is clamped to about 10-20V, referenced to the anode voltage. The clamped voltage powers a differential amplifier for the detecting if the anode voltage is greater than the cathode voltage. The capacitor is charged to the clamped voltage during normal operation of the ideal diode by controlling the conductivity of a second transistor coupled between the cathode and the capacitor, enabling the circuit to be used with a wide range of frequencies and voltages. All voltages applied to the differential amplifier are equal to or less than the clamped voltage.

Abstract: A PHY is coupled across split primary windings of an isolation transformer for differential data transmission and reception between PHYs and for DC isolation. Positive and negative low impedance terminals of a DC power supply are coupled to first and second secondary windings of the transformer as split center taps of the transformer. Respective ends of the wires in the wire pair are coupled to the other ends of the secondary windings. Therefore, the power supply conducts DC current through the secondary windings, while the differential data signals also flow through the secondary windings, generating corresponding differential data signals at the inputs to the PHY. The transformer also attenuates common mode noise. Therefore, the circuit makes multi-use of the isolation transformer, allowing fewer components to be used for the DC coupling, wire termination, and common mode noise cancellation.

Abstract: In one embodiment, a master device has a first port and a second port and initially applies a DC voltage only to the first port. A plurality of slave devices, each have a third port and a fourth port, are serially connected to the master device in a ring, via conductors, starting at the first port and ending at the second port. The conductors simultaneously carry the DC voltage and differential data. Each slave device, after performing a detection routine, then sequentially applies the DC voltage to the adjacent downstream slave device in a first direction around the ring. If the master does not detect the presence of the DC voltage at its second port, the master device applies the DC voltage to both the first port and the second port to sequentially power up the slave devices in both directions around the ring of slave devices.

Abstract: A synchronous converter that includes a power source, an inductor, an output terminal, and a control circuit. The control circuit may include: an electronic energizing switch that, when activated, delivers energy from the power source to the inductor; an electronic de-energizing switch that, when activated, delivers energy from the inductor to the output terminal, the electronic de-energizing switch including a body diode; and an electronic pull-down switch that, when activated, turns off the electronic de-energizing switch, redirects current flowing though the body diode of the electronic de-energizing switch, and removes charge from the body diode of the electronic de-energizing switch. The electronic energizing switch and the electronic de-energizing switch may never both be activated at the same time.

Abstract: A hybrid power converter circuit includes a switched-capacitor power converter stage and a pulse-width modulation (PWM) or resonant output circuit coupled to a switching node of the switched-capacitor power converter stage. In particular, the PWM or resonant output circuit can include a transformer having a primary winding and a secondary winding magnetically coupled to each other, and the secondary winding is coupled to the output node of the power converter. The switched-capacitor power converter stage is coupled between the input node of the power converter and the primary winding of the transformer, and includes capacitors and switches configured to connect the capacitors to the input node during a first phase of operation and connect the capacitors to the primary winding of the transformer of the PWM or resonant output circuit during a second phase of operation.

Abstract: A predicted ripple in the feedback voltage of a switching converter is generated, based on the ripple over a certain number of recent switching cycles. The DC portion of the feedback voltage is filtered out. This predicted feedback voltage ripple is then added to a fixed reference voltage to create a compensated reference voltage. The compensated reference voltage is applied to the non-inverting input of an error amplifier, and the feedback voltage (having a DC component and ripple) is applied to the inverting input of the error amplifier. Thus, substantially the same ripple component is applied to both inputs and cancels out. Therefore, the output of the error amplifier is not affected by the ripple in the feedback voltage, and a non-rippling control voltage is generated by the error amplifier. As a result, the gain-bandwidth product of the converter can be increased for faster response to transients.

Abstract: A composite transconductance amplifier is formed using a single transconductance amplifier with its output connected to a load via one or more resistors in series. The single transconductance amplifier has a linear transconductance (gm). As the current through the series resistors is increased, the voltage drops across the nodes of the resistors increase. Control terminals of separate drive circuits are connected to the various nodes and successively turn on as the current from the single transconductance amplifier slews more positive. Thus, the effective gm of the composite transconductance amplifier is based on the gm of the single transconductance amplifier and the currents contributed by the successively enabled drive circuits. Therefore, the gm is nonlinear. Pull-down drive circuits are also connected to the resistor nodes to successively pull down the current as the output from the single transconductance amplifier slews negative. The composite transconductance amplifier has low quiescent current.

Abstract: In a method performed by a PoE system, a PSE provides data and operating voltage over Ethernet wires to a PD. Before the full PoE voltage is supplied, the PSE generates a low current signal received by the PD. A circuit in the PD, connected across its input terminals, has a characteristic analog response to the PSE signal corresponding to the PD's PoE requirements, such as whether the PD is a Type 1 or Type 2 PD. The circuit may be a certain value capacitor, zener diode, resistor, or other circuit. The PSE may generate a fixed current, fixed voltage, or time varying signal. Upon the PSE sensing the magnitude of the analog signal response at a particular time, the PSE associates the response with the PoE requirements of the PD. The PSE then applies the full PoE voltage in accordance with the PD's PoE requirements.

Abstract: The invention pertains to systems where DC power is supplied by a PSE to a PD, such as over differential data wire pairs. IEEE standards require a minimum current to be drawn from the PD in order for the PSE to continue supplying the DC voltage. If the PD is in a low power mode, the PSE will normally discontinue supplying the DC voltage, which then requires a new detection and classification routine for powering up again. To avoid this, a “maintain power signature” controller provides a periodic current pulse by a current source connected between the PD input and the PD's full bridge rectifier. Any droop in the DC voltage that reverse biases the full bridge rectifier while the PD is in its low power mode will not affect the current pulse, so the PSE continues to supply the DC voltage.

Abstract: In one embodiment, a pass MOSFET is coupled in series between an input voltage and a load, and a bypass capacitor is connected in parallel with the load. In response to a voltage step across the MOSFET, the MOSFET is adaptively controlled to conduct an in-rush current of 2ICL=2IL during the bypass capacitor 12 charging time, where ICL is the capacitive current and IL is the load current. This optimizes the in-rush current to achieve a minimum peak temperature of the MOSFET. In one embodiment, a ramp capacitor connected to the drain of the MOSFET is part of a feedback path that tracks the MOSFET drain voltage to control the gate voltage.

Abstract: A PoDL system includes a PSE connected via a wire pair to a PD, where differential data and DC power are transmitted over the same wire pair. Typically, low voltage/current detection and classification routines are required upon every powering up of the system to allow the PD to convey its PoDL requirements to the PSE. Various techniques are described that simplify or obviate such start-up routines or enable increased flexibility for the PoDL system. Such techniques include: ways to specify a particular PD operating voltage; ways to disable the PD's UVLO circuit during such routines; using opposite polarity voltages for the two routines; using voltage limiters or surge protectors to convey the PoDL information; detecting loop resistance; using a PSE memory to store previous results of the routines; and powering the PD communication circuit using the wire pair while the PD load is powered by an alternate power source.