Abstract: A novel system is offered for supplying power from an input node to a load coupled to an output node. The system may have multiple switches coupled between the input node and the output node. One or more limiting circuits may be configured for controlling the switches so as to limit outputs of the switches. For example, the limiting circuits may limit current through the respective switches. One or more timers may set a delay period for indicating a fault condition after the limiting is initiated.

Abstract: Methods and systems of controlling a switched capacitor converter are provided. Upon determining that a voltage across a flying capacitor is above a first threshold, a first current is drawn from a first terminal of the flying capacitor by a first current source, and a second current is provided to a second terminal of the flying capacitor by a second current source. Upon determining that the voltage across the flying capacitor is below a second threshold, the first current is provided to the first terminal of the flying capacitor by the first current source, and the second current is drawn from the second terminal of the flying capacitor by the second current source. Upon determining that the voltage across the flying capacitor is above the second threshold and below the first threshold from the reference voltage, the first and second current sources are turned OFF.

Abstract: In the example of a voltage regulator outputting a negative voltage, its feedback voltage will also be negative. The feedback voltage is typically created using a resistor divider. A controller IC is powered by only a positive voltage and receives the negative feedback voltage at a high impedance input of an inverting amplifier. Therefore, the inverting amplifier does not load the resistor divider, resulting in an accurate regulated output voltage. The inverting amplifier converts the negative feedback voltage to a positive feedback voltage for further processing by the controller IC. An error amplifier and a power good monitor receive both the original feedback voltage and the inverted feedback voltage and use whichever feedback voltage is the more positive one. Therefore, the controller IC may be used in voltage regulators that generate either negative or positive output voltages.

Abstract: An integrated circuit includes (a) an analog-to-digital converter operated according to a first clock signal; and (b) a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a frequency that is different from a frequency of the first clock signal, such that a noise level introduced by the charge pump into the analog-to-digital converter is less than the average noise level over a predetermined range of frequencies for the second clock signal. The integrated circuit may further include a clock divider circuit (e.g., a programmable clock divider) that generates both the first clock signal and the second clock signal.

Abstract: A predicted ripple in the feedback voltage of a switching converter is generated, based on the ripple over a certain number of recent switching cycles. The DC portion of the feedback voltage is filtered out. This predicted feedback voltage ripple is then added to a fixed reference voltage to create a compensated reference voltage. The compensated reference voltage is applied to the non-inverting input of an error amplifier, and the feedback voltage (having a DC component and ripple) is applied to the inverting input of the error amplifier. Thus, substantially the same ripple component is applied to both inputs and cancels out. Therefore, the output of the error amplifier is not affected by the ripple in the feedback voltage, and a non-rippling control voltage is generated by the error amplifier. As a result, the gain-bandwidth product of the converter can be increased for faster response to transients.

Abstract: Circuits and techniques are described for detecting a ground fault leak between the PSE and the PD. Prior to PoDL voltage being applied to the PD, a test switch is temporarily closed for sensing a voltage drop in a loop between the positive terminal of the PSE voltage source and any ground leakage path between the PSE and the PD. If the resistance of the ground leakage path is below a certain threshold, a fault is declared. A similar test may be performed without a test switch by supplying a known test current through the loop and sensing the voltage drop. Another test is to connect the positive terminal of the PSE voltage source to the loop and sense the resulting current. After the full PoDL voltage is applied to the PD, a ground fault may be detected by sensing the equivalence between the source and return PSE currents.

Abstract: Multiple termination impedance values are provided in a switchable termination circuit so as to accommodate multiple transmission line characteristics. In one example, a termination matching circuit includes first and second nodes, a series interconnection of a first switch and a first impedance coupled between the first and second nodes, and another series interconnection of a second switch and a second impedance coupled between the first and second nodes. First and second control circuits respectively control the first and second switches such that a selectable impedance is provided between the first and second nodes through selective activation of the first and second switch devices by the first and second control circuits. In another example, additional nodes and resistors are provided to provide further termination impedance values.

Abstract: A system for synchronizing nodes in a wireless network comprises a first node and a second node. The first node comprising a transmitter, a receiver, and a first time keeper. The second node comprising a transmitter, a receiver, a second time keeper, a timing error measurer for making a timing error measurement between the first time keeper and the second time keeper. The second timekeeper is adjusted to target minimizing the timing error measurement.

Abstract: In a method performed by a PoE system, a PSE provides data and operating voltage over Ethernet wires to a PD. Before the full PoE voltage is supplied, the PSE generates a low current signal received by the PD. A circuit in the PD, connected across its input terminals, has a characteristic analog response to the PSE signal corresponding to the PD's PoE requirements, such as whether the PD is a Type 1 or Type 2 PD. The circuit may be a certain value capacitor, zener diode, resistor, or other circuit. The PSE may generate a fixed current, fixed voltage, or time varying signal. Upon the PSE sensing the magnitude of the analog signal response at a particular time, the PSE associates the response with the PoE requirements of the PD. The PSE then applies the full PoE voltage in accordance with the PD's PoE requirements.

Abstract: A current mode switching converter includes a transistor switch, an inductor configured to conduct a ramping inductor current as the transistor switch is turned on and off at a particular duty cycle, and an inductor current sensor generating a current sense signal. The current sense signal has an up-slope portion and a down-slope portion. A separate ramp generator generates a ramp voltage for each switching cycle. A slope compensation circuit compensates the ramp voltage, depending on the duty cycle and other factors, to create a compensated ramp voltage. The compensated ramp voltage is then summed with the current sense signal to create a compensated current sense signal for a comparator. The slope compensation circuit forces the compensated current sense signal to have an up-slope greater than an absolute value of its down-slope at least for duty cycles greater than 50% to rapidly dampen perturbations in the duty cycle.

Abstract: A method and system of providing an active differential resistor. The active differential resistor includes a diode having a first node and a second node. There is a capacitor coupled in series between the first node of the diode and an input of the active differential resistor. There is a current source coupled across the first node and the second node of the diode and configured to forward bias the diode such that a Johnson-Nyquist noise of the active differential resistor is replaced by a shot noise.

Abstract: A PoDL system includes a PSE connected via a wire pair to a PD, where differential data and DC power are transmitted over the same wire pair. Typically, low voltage/current detection and classification routines are required upon every powering up of the system to allow the PD to convey its PoDL requirements to the PSE. Various techniques are described that simplify or obviate such start-up routines or enable increased flexibility for the PoDL system. Such techniques include: ways to specify a particular PD operating voltage; ways to disable the PD's UVLO circuit during such routines; using opposite polarity voltages for the two routines; using voltage limiters or surge protectors to convey the PoDL information; detecting loop resistance; using a PSE memory to store previous results of the routines; and powering the PD communication circuit using the wire pair while the PD load is powered by an alternate power source.

Abstract: A system includes a master and a slave coupled via a wire pair for transmitting differential data. The master and slave are each powered by a local DC power supply. In a normal mode, a DC voltage and differential data are supplied over the same wire pair. The differential data is processed by a PHY AC-coupled to the wire pair. To enter a low power sleep mode, such as due to a temporary non-use of the system, the master interrupts the DC voltage on the wire pair, which signals to the slave to enter the sleep mode. The system is woken up by reapplying the DC voltage to the wire pair to signal to the slave to wake up. Only the DC path, and not the data path, is used for signaling the sleep mode and awake mode, so the data path can be disabled to conserve power.

Abstract: A method and system of an analog to digital conversion having an exponential result are provided. An analog input signal is received by the ramp ADC. The analog input signal is converted into an N-bit digital signal having a linear relationship with the analog input signal. An internal gated clock signal is generated based on the received first clock signal. The gated clock signal is used as an input to an M-bit register. An output of the M-bit register is multiplied by a predetermined factor. The product of the multiplication is provided as an input to the M-bit register. The output of the M-bit register provides an M-bit output having an exponential relationship with the analog input signal.

Abstract: A PoDL system includes a PSE supplying DC power and Ethernet data over a single twisted wire pair to a PD. Prior to coupling the DC voltage source to the wire pair, the PD needs to receive sufficient power to perform a detection and classification routine with the PSE to determine whether the PD is PoDL-compatible. The PSE has a low current, pull-up current source coupled to a first wire in the wire pair via a first inductor. This pull-up current charges a capacitor in the PD to a desired operating voltage, and the operating voltage is used to power a PD logic circuit. The PD logic circuit and a PSE logic circuit then control pull-down transistors to communicate detection and classification data via the first wire. After the handshaking phase, the PSE then applies the DC voltage source across the wire pair to power the PD for normal operation.

Abstract: An anemometer and method for analyzing fluid flow is described. In one embodiment, a transistor sensor is heated by applying power to cause its base-emitter junction to rise from an ambient first temperature to a second temperature. The power is removed, and the Vbe is measured at intervals as the junction cools. The Vbe equates to a temperature of the junction. The temperature exponentially decreases, and the time constant of the decay corresponds to the fluid flow velocity. A best fit curve analysis is performed on the temperature decay curve, and the time constant of the exponential decay is derived by a data processor. A transfer function correlates the time constant to the fluid flow velocity. The transistor is thermally coupled to a metal rod heat sink extending from the package, and the characteristics of the rod are controlled to adjust the performance of the anemometer.

Abstract: A Power Over Data Lines (PoDL) system includes Power Sourcing Equipment (PSE) supplying DC power and differential Ethernet data over a single twisted wire pair to a Powered Device (PD). Due to start-up perturbations, PD load current variations, and other causes, dV/dt noise is introduced in the power signal. Such noise may be misinterpreted as data unless mitigated somehow. Rather than increasing the values of the passive filtering components conventionally used for decoupling/coupling the power and data from/to the wire pair, active circuitry is provided in the PSE, PD, or both to limit dV/dt in the power signal. Such circuitry may be implemented on the same chip as the PSE controller or PD controller. Therefore, the sizes of the passive components in the decoupling/coupling networks may be reduced.

Abstract: A method and system of counting coulombs drawn from a power source by a load. A reference current source regulates the current drawn by the load at any given time to be either zero or a predetermined fixed amount. A comparator controls a time the switch is closed and open. When the switch is closed, coulombs are allowed to be drawn from the power source, and prevented to be drawn when the switch is open. An oscillator generates a clock signal during the time the switch is closed. A counter counts the number of clock cycles from the clock signal during the time the switch is closed. The count is provided as a signal at a second output of the coulomb counter.

Abstract: A flipchip may include: a silicon die having a circuit side with solder bumps and a non-circuit side; a leadframe attached to the solder bumps on the circuit side of the silicon die; a heat spreader attached to the non-circuit side of the silicon die; and encapsulation material encapsulating the silicon die, a portion of the leadframe, and all but one exterior surface of the heat spreader. The leadframe may have NiPdAu plating on the portion that is not encapsulated by the encapsulation material and no plating on the portion that is attached to the solder bumps.

Abstract: A power interface device includes a main switching converter, an auxiliary switching converter, and a feedback sense circuit. The main switching converter is coupled to an input terminal and an output terminal and configured to operate at a first switching frequency to source a low frequency current from the input terminal to the output terminal. The auxiliary switching converter is coupled to the input terminal and the output terminal in parallel with the main switching converter and configured to operate at a second and higher switching frequency than the first switching frequency to source a fast transient high frequency current from the input terminal to the output terminal.