Abstract: The invention described herein utilizes devices under test (DUTs) outfitted with stored, predefined test sequences, testers equipped with vector-signal generation (VSG) and vector-signal analysis (VSA) functionality, and novel methods for combining loopback and single-ended test functions in order to obtain higher testing efficiency for DUTs using Bluetooth or other time-division duplex (TDD) based communications.

Abstract: Signal conversion circuitry and method for converting a multiple input, multiple output (MIMO) packet data signal transmission to a plurality of complex data samples for processing by shared test equipment, e.g., a single vector signal analyzer (VSA).

Abstract: Execution of a block test “retry” in a test environment with each block in the test sequence sent after the tester has determined that the previous block of data packets has met one or more prescribed test criterion. If a block sent by the DUT has not met the test criterion, a retry sequence is initiated to re-test the block. In another embodiment, a block test “retry” is executed where each block in the test sequence is sent and analysis of previously sent blocks is done in parallel with the sending of a subsequent block. If a previous block has not met the test criterion, a retry sequence is initiated whereby the tester and DUT step back to the block that failed to meet the test criterion and retry that block. If the retry meets test criterion, testing continues by resuming with the next untested block in the sequence.

Abstract: Circuitry and method for reduce test time for wireless signal systems by using dynamic adaptive correction of DC offsets generated by the test instrument. The data signal is sampled for downstream processing including during pre-, inter-, or post-packet time intervals where no packet-data signal is occurring and where the device's power amplifier is turned off. The sampled data signal is measured for a DC offset occurring during these inter-packet time gaps. Compensating DC offset values are stored in a table indexed by frequency, gain and temperature range. When a subsequent test is carried out at that frequency, gain, and temperature range, the stored compensation value is used to correct the signal. DC offsets continue to be measured, stored and applied to captured signals, continuously refining the compensation values and decreasing the need for time-intensive calibrations. When a measured DC offset exceeds pre-determined limits, the instrument undergo a calibration step.

Abstract: A local oscillator (LO) of a test system is set to an initial frequency whereupon a device under test (DUT) transmits a radio frequency (RF) signal to the test system. Characteristics of the RF signal are measured with the test system and used to identify magnitudes and frequencies of spurious signal products. The LO of the test system is reset to one or more subsequent frequencies that are offset from the initial frequency. One or more subsequent RF signals are transmitted from the DUT to the test system, with the DUT maintaining its original signal settings. Characteristics of the subsequent RF signals are measured with the test system and used to identify magnitudes and frequencies of spurious signal products for each of the subsequent LO frequencies. The spurious signal products that have shifted in frequency for each of the subsequent LO frequencies as self-generated signal products can then be identified.

Abstract: An apparatus for testing a communication circuit includes a dynamic range module. The dynamic range module includes signal strength adjustment module and a control module. The signal strength adjustment module adjusts a peak signal strength of test packets transmitted according to a predetermined test sequence. The control module selectively controls the signal strength adjustment module to adjust the peak signal strength based on the predetermined test sequence.

Abstract: Circuitry and method for reduce test time for wireless signal systems by using dynamic adaptive correction of DC offsets generated by the test instrument. The data signal is sampled for downstream processing including during pre-, inter-, or post-packet time intervals where no packet-data signal is occurring and where the device's power amplifier is turned off. The sampled data signal is measured for a DC offset occurring during these inter-packet time gaps. Compensating DC offset values are stored in a table indexed by frequency, gain and temperature range. When a subsequent test is carried out at that frequency, gain, and temperature range, the stored compensation value is used to correct the signal. DC offsets continue to be measured, stored and applied to captured signals, continuously refining the compensation values and decreasing the need for time-intensive calibrations. When a measured DC offset exceeds pre-determined limits, the instrument undergo a calibration step.

Abstract: A system and method of providing driver software to a test controller to facilitate testing by a wireless transceiver tester of a device under test (DUT). Using the wireless transceiver tester, executable tester instructions are accessed from one or more computer readable media and in accordance therewith bi-directional signal communications are established between the wireless transceiver tester and the test controller, and between the wireless transceiver tester and the DUT. Further accessed are executable driver instructions, including a plurality of executable driver program instructions for driving at least one of the wireless transceiver tester and the DUT, which are communicated to the test controller.

Abstract: A system and method for testing a data packet signal transceiver in which multiple network addresses (e.g., media access control, or MAC, addresses) are used to establish synchronization of the device under test and the test equipment controlling the test. In accordance with an exemplary embodiment, synchronization is established using a first MAC address, following which testing is conducted using a second MAC address.

Abstract: A method and system for testing packet error rate in electronic devices by transmitting a series of data packets from a testing device to a device under test (DUT) and setting a predefined number of received error-free data packets; evaluating whether a number of data packets from the series of data packets received error-free by the DUT equals the predefined number of received error-free data packets and transmitting additional data packets from the testing device to the DUT, at a power level known to produce zero received-packet errors in a correctly operating DUT, if the number of data packets from the series of data packets received error-free by the DUT does not equal the predefined number of received error-free data packets.

Abstract: A system and method is disclosed for testing a communication device. In accordance with the described invention, a single vector signal generator (VSG) is utilized to test manufactured 2x2, 3x2 and 4x2 MIMO wireless devices to identify possible manufacturing defects that may impair or disable the device under test (DUT) receivers from properly receiving constituted MIMO TX signals and accurately decoding the bits/symbols conveyed by transmitted TX signals. Disclosed embodiments may include a VSG coupled to a DUT. The VSG being configured to transmit data packets as a first codeword and a second codeword, wherein the VSG includes software and hardware architecture to manipulate the first codeword and the second codeword as emulated first and second waveforms, wherein the first waveform is different than the second waveform. The DUT being configured to receive the emulated first and second waveforms as prescribed signals from the VSG.

Abstract: A system for testing a communication device includes a testing module, a measurement module, and a control module. The testing module transmits one or more first test signals based on a first test sequence. The measurement module acquires test data by receiving one or more second test signals that are based on the one or more first test signals. The control module initiates the first test sequence in response to receiving a start test signal from an analysis system. The control module transfers the test data to the analysis system in response to a transfer data request. The control module initiates a second test sequence while the analysis system is analyzing the test data. The testing module generates and transmits one or more third test signals based on the second sequence when the second test sequence has been initiated.

Abstract: Signal conversion circuitry and method for converting a multiple input, multiple output (MIMO) packet data signal transmission to a plurality of complex data samples for processing by shared test equipment, e.g., a single vector signal analyzer (VSA).

Abstract: Methods for measuring the sensitivity of a data packet signal receiver are provided by varying the power level or modulation or both of a received data packet signal in a predetermined controlled sequence of data packet signals.

Abstract: A digital communications test system and method for testing a plurality of devices under test (DUTs) in which multiple sets of a single vector signal analyzer (VSA) and single vector signal generator (VSG) can be used together to perform error vector magnitude (EVM) measurements for one or more DUTs in parallel, including one or more of composite, switched and multiple input multiple output (MIMO) EVM measurements. This allows N pairs of a VSA and VSG to test N DUTs with NxN MIMO in substantially the sane time as a single VSA and VSG pair can test a single DUT, thereby allowing a substantial increase in testing throughput as compared to that possible with only a single VSA and VSG set.

Abstract: Methods for measuring the sensitivity of a data packet signal receiver are provided by varying the power level or modulation or both of a received data packet signal in a predetermined controlled sequence of data packet signals.

Abstract: A digital communications test system and method for testing a plurality of devices under test (DUTs) in which multiple sets of a single vector signal analyzer (VSA) and single vector signal generator (VSG) can be used together to perform error vector magnitude (EVM) measurements for one or more DUTs in parallel, including one or more of composite, switched and multiple input multiple output (MIMO) EVM measurements. This allows N pairs of a VSA and VSG to test N DUTs with N×N MIMO in substantially the sane time as a single VSA and VSG pair can test a single DUT, thereby allowing a substantial increase in testing throughput as compared to that possible with only a single VSA and VSG set.

Abstract: A digital communications test system and method for testing a plurality of devices under test (DUTs) in which multiple sets of a single vector signal analyzer (VSA) and single vector signal generator (VSG) can be used together to perform error vector magnitude (EVM) measurements for one or more DUTs in parallel, including one or more of composite, switched and multiple input multiple output (MIMO) EVM measurements. This allows N pairs of a VSA and VSG to test N DUTs with N×N MIMO in substantially the sane time as a single VSA and VSG pair can test a single DUT, thereby allowing a substantial increase in testing throughput as compared to that possible with only a single VSA and VSG set.

Abstract: A method and system for testing a wireless data packet transceiver as a device under test (DUT) adapted to operate in conformance with a wireless signal standard such that a transmitted signal, when received by an intended receiver, is to result in a responsive signal transmission acknowledging such signal reception. During testing, responsive signal transmissions, e.g., acknowledgement signals, are withheld by the test system until after a predetermined number of data packets have been captured from the DUT, until a predetermined time interval has passed, or until data packets at a predetermined number of data rates have been captured from the DUT.

Abstract: A method and apparatus for testing multiple data signal transceivers substantially simultaneously with a common transceiver tester by analyzing previously captured data signal transmissions from some of the data signal transceivers while continuing to capture further data signal transmissions from additional ones of the data signal transceivers.