Abstract: A method and system for predicting delay of a multi-million gate sub-micron ASIC design is disclosed. The method and system include automatically partitioning a netlist into at least two logic cones, and running respective instances of a delay prediction application on the logic cones on at least two computers in parallel.

Abstract: A memory cell architecture is provided herein for increasing memory speed, performance and robustness within a highly compact memory cell layout. Though only a few embodiments are provided herein, a feature common to all embodiments includes a novel means for sharing one or more contact structures between vertically adjacent memory cells. In particular, one or more contact structures may be shared unequally between two vertically adjacent memory cells for reducing a vertical dimension, or length, of the memory cell. Other features are disclosed for producing the highly compact memory cell layout. The various features of the present invention may be combined to produce high-performance, high-density memory arrays.

Abstract: An apparatus generally comprising a plurality of processors, a trace circuit, and a connector circuit. The trace circuit may be configured to present information at a port for debugging software in a selected processor of the processors. The connector circuit may be configured to (i) couple the trace circuit to the selected processor in response to a select signal and (ii) transfer the information from the selected processor to the trace circuit while the selected processor is executing the software.

Abstract: A system identifies one or more devices having faults in a communication loop. The system includes an interface, a decision module, and a connection processor. The interface is configured for sending requests for information to each device of the communication loop and for receiving responses to the requests. The devices may include computer disk drives for use in a storage system. The requests may include Read-Link Status (RLS) commands sent to the computer disk drives. The RLS commands may provide diagnostics of the disk drives connected to the loop. The decision module is communicatively connected to the interface for weighting the responses of each device to identify the devices having the faults. The responses may be weighted based on the relative potential for disrupting operability of the system. The communication loop may include an FC loop that allows communications between a host system and the computer disk drives.

Abstract: An apparatus for receiving and processing an electrical signal in the form of a pulse train comprising a plurality of pulses. The apparatus generally comprises a processor, a memory and a timer. The timer may be configured to generate a respective value representative of the positions of each leading and trailing edge of each pulse in the pulse train. The memory may be configured to receive the value and write the value. The timer may be configured to generate an interrupt signal following receipt of the trailing edge of the last pulse in the pulse train and apply the interrupt signal to the processor. The processor may read the values stored in the memory for decoding the pulse train in response to said interrupt signal.

Abstract: The present invention provides an apparatus and a method for embedding information from a first configuration data set having data structures into an embedded processing system, wherein embedding the information maintains user-defined variables. Embedding information includes comparing a first identifier from the first configuration data set with a second identifier from a second configuration data set having data structures to determine if the first identifier differs from the second identifier. In response to a determination of the first identifier differing from the second identifier, a decision is made to merge the first configuration data set with the second configuration data set to form a merged configuration data set. Afterwards, the merged configuration data set is written to the embedded processing system, wherein the merged configuration data set includes maintained user-defined variables.

Abstract: A heterogeneous integrated circuit having a digital signal processor and at least one programmable logic core. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. Memory sharing is controlled to allocate the full bandwidth of the DSP memory to the PLCs and other DMA devices in proportion to their operating speeds. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers.

Abstract: A method and system is disclosed for inserting dummy metal into a circuit design, which includes a plurality of objects and clock nets. Aspects of the invention include identifying free spaces on each layer of the chip design suitable for dummy metal insertion, wherein the free spaces are referred to as dummy regions. Thereafter, the dummy regions are prioritized such that the dummy regions located adjacent to clock nets are filled with dummy metal last. In a preferred embodiment, the dummy regions are further prioritized such that the dummy regions adjacent to wider clock nets are filled with dummy metal after dummy regions that are located adjacent to narrower clock nets.

Abstract: The present invention provides a method and apparatus for reconfiguring a memory array. Aspects of the present invention include fabricating the memory array as at least one row of single-port cells up to a first metal layer. A split word line having first and second word lines is coupled to the single-port cells in each row, wherein the first word line is patterned in the first metal layer, and the second word line is patterned in a second metal layer. The split word line is further coupled to a spacer cell in the row. The method and apparatus further include programming the memory array into custom configurations based on whether the first and second word lines are connected over the spacer cell, or whether the first and second word lines are left unconnected.

Abstract: An interface system capable of providing pre-emptive arbitration among multiple agents comprises an interface including at least a first agent and a second agent which share the interface for transferring data, the second agent having priority over the first agent for access to the interface. A pre-emptive arbiter provides arbitration between the first agent and the second agent when at least one of a first transfer request signal is asserted by the first agent for requesting access to the interface by the first agent and a second transfer request signal is asserted by the second agent for requesting access to the interface by the second agent. The pre-emptive arbiter is capable of synthesizing a transfer completion signal on the interface for preempting access of the first agent to the interface so that access may be granted to the second agent.

Abstract: A method of recording data on a recording medium includes mapping the data to a set of write symbols wherein each write symbol represents more than one bit of the data. The set of write symbols is defined by defining a set of variable write parameters; generating a plurality of candidate write symbols that specify different values for the variable write parameters; generating a plurality of readout waveforms produced by the plurality of candidate write symbols; analyzing the readout waveforms to determine desired set of readout waveforms; and selecting selected ones of the plurality of candidate write symbols that correspond to the desired readout waveforms to be included in the set of write symbols. The data is written to the medium using the write symbols.

Abstract: A method of generating a physical netlist for an integrated circuit design includes steps of: (a) receiving as input a representation of a core cell for a hierarchical integrated circuit design; (b) generating a physical netlist for a core cell model tile that maps logical ports of the core cell to physical ports of the core cell model tile; (c) including values for parasitic resistances connecting the logical ports of the core cell to the physical ports of the core cell model tile in the physical netlist for the core cell model tile; (d) connecting a hierarchical array of core cell model tiles so that the physical ports of each core cell model tile are connected to one another inside the array or mapped to an input/output port of the hierarchical array of core cell model tiles; and (e) generating as output a physical netlist of the hierarchical array of core cell model tiles.

Abstract: A semiconductor comprising a plurality of first building blocks arranged in one or more first rows and a plurality of second building blocks arranged in one or more second rows. The one or more second rows are interleaved with the one or more first rows and the first building blocks and the second building blocks each provide a segment of horizontal and a segment of vertical routing.

Abstract: According to one embodiment, a method of testing an integrated circuit is provided. A reference voltage is coupled to each of a first and second comparator integrated on the chip. A supply voltage is compared to the reference voltage in a comparator to determine overvoltage or undervoltage conditions. The results of the comparison are stored and sizing and placing of at least one decoupling circuit in the circuit design is made based on the stored determinations.

Abstract: The present invention is directed to a method and apparatus to find an optimal unification substitution for formulas in a technology library. In an exemplary aspect of the present invention, a method for finding an optimal unification substitution for formulas in a technology library during integrated circuit design may include the following steps: (a) receiving input including a list L of pairs of formulas in standard form, a set S of substitutions for variables, a right part e(x1, . . . , xp) of an identity, and an information I={t, h, r, a, p} on best application; (b) when the list L is not empty, extracting and removing first pair (ƒ?(A?1, . . . , A?n?), g?(B?1, . . . , B?m?)) from the list L; (c) removing head inverters and buffers from formulas ƒ?(A?1, . . . , A?n?) and g?(B?1, . . . , B?m?)) and obtaining a pair (ƒ(A1, . . . , An), g(B1, . . . , Bm)); (d) when the ƒ is a commutative operation but neither a variable nor constant, and when heads of the formulas ƒ(A1, . . . , An) and g(B1, . . .

Abstract: A method and apparatus for improving resolution in photolithography. The method includes steps of mapping a first phase onto a first mask, mapping a second phase onto a second mask, and mapping a trim onto the first mask or second mask (or both). Specifically, the first mask may include Phase1 mapped to 0/180 phase, and the second mask may include Phase2 and trim mapped to 0/180 phase. A set of masks consistent with the foregoing is provided.

Abstract: A phase-locked loop within an integrated circuit assembly is provided. The phase-locked loop includes a plurality of subcells of semiconductor devices arranged in a base layer pattern on base layers of the integrated circuit assembly. One or more metal layers are formed over and interconnect the plurality of semiconductor devices in a metallization pattern. The phase-locked loop has an output frequency range that is changeable with a change to the metallization pattern without a corresponding change to the base layer pattern.

Abstract: A method of constructing a circuit for a Boolean function includes receiving as input a Boolean function of a number n of input variables wherein the number n of input variables may be varied over a range; generating at least two intermediate functions comprising sub-functions of the Boolean function wherein zero or one is substituted for all but two of the number n of input variables; and generating a selected output of the Boolean function of the number n of input variables from only two of the intermediate functions.

Abstract: Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.

Abstract: A system and method for handling shared resource writes arriving via non-maskable interrupts in single thread non-mission critical system with limited memory space includes a queue for providing temporary storage of a write request. The queue is accessible by lower or higher priority processes for the servicing of the write requests. Upon completion of service to the write requests the system returns control to the standard operations of the single thread system.