Abstract: Provided are methods and apparatuses for decoding input data by using a single decoder for decoding a first set of symbols and then, after those decoded symbols have been interleaved, using the same decoder for decoding the decoded and interleaved first set of symbols together with a second set of symbols. Also provided are methods and apparatuses for decoding input data by using multiple read/write means for controlling the storage and reading of data so as to interleave and/or de-interleave data simultaneously with data buffering.

Abstract: Disclosed is a system and method for using a mirrored disk as a bootable backup disk for a computer system. A mirroring routine may be used to create a backup disk, then discontinued during normal operations. Should a problem occur with the main disk, the computer system may be rebooted using the backup disk and the main disk can be rebuilt from the backup disk using the mirroring routine. The system and method may be applied to two disk systems and various multiple-disk arrays such as RAID systems.

Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.

Abstract: An apparatus comprising one or more groups of boundary scan cells, one or more group buffers, one or more repeater buffers and a controller. The group buffers may be coupled to each of the groups of boundary scan cells. The repeater buffers may be coupled in series with the group buffers. The controller may be coupled to the groups of boundary scan cells through the group buffers and the repeater buffers. The apparatus may be configured to buffer the groups of boundary scan cells to reflect an order of I/Os around the apparatus.

Abstract: The present invention is directed to a comprehensive design flow system. A system and method are provided that provide a comprehensive system to introduce a metamethodology that integrates EDA design tools into a manageable and predictable design flow. A method of designing an integrated circuit may include accessing a design utility operating on an information handling system, displaying a dynamic template on a display device of an information handling system, wherein the dynamic template implements at least two symbols displayable on a display device, in which the at least two symbols each correspond to a respective EDA tool, and arranging the at least two symbols displayed on the display device. The at least two symbols are arranged to indicate an interrelationship of the EDA tools in a design process of an integrated circuit.

Abstract: A method and apparatus for generating a CRC (cyclic redundancy check)/parity error in network environment. A SCSI (small computer systems interface) bus expander such as an Ultra320 bus expander or the like is added between a sending device and a receiving device. The sending device-receiving device pair may execute a training session to determine the skew compensation. During the training session, the SCSI bus expander may figure out timing differences due to skew and adjusts the timing of each data signal to compensate for skew. For each data signal, a compensated time may be obtained. The compensated time may then be modified through a JTAG (Joint Test Action Group) port of the SCSI bus expander. The compensated times may be adjusted such that a CRC/parity error is generated on every I/O (input/output) or just some I/Os to the receiving device.

Abstract: A data bus system transfers words and word portions on a data bus between master devices and slave devices. A size bus carries a size code in fixed-byte format that identifies a number of bytes being transferred in one or more words and/or word portions of a transaction. A byte-enable bus carries a byte-enable code that identifies valid bytes of a word. An interface decodes the byte-enable codes to size codes and, where an odd-byte byte-enable code is decoded, it decodes the odd-byte byte-enable code to a plurality of size codes.

Abstract: A method for forming damascene interconnect copper diffusion barrier layers includes implanting calcium into the sidewalls of the trenches and vias. The calcium implantation into dielectric layers, such as oxides, is used to prevent Cu diffusion into oxide, such as during an annealing process step. The improved barrier layers of the present invention help prevent delamination of the Cu from the dielectric.

Abstract: Provided are methods and composition for forming diamond metal-filled patterns above an integrated circuit substrate. A metal layer is formed above the integrated circuit substrate, which is then patterned such that a metal line is created. A plurality of diamond-shaped metal regions are then formed at least one of above and adjacent to the metal line formed on the integrated circuit substrate such that the density of metal on the integrated circuit substrate is greater than a specified density, thereby ensuring that a surface of dielectric formed above the metal line remains substantially planar after application of CMP to the dielectric layer.

Abstract: The present invention is directed to a system and method for heterogeneous multiprocessor reference design. In an aspect of the present invention, a method of designing a multiprocessor integrated circuit may include receiving a specification for an integrated circuit having multiprocessors, the specification having a desired functionality. Functional components are chosen which provide the desired functionality of the received specification. The functional components are implemented in a modular multiprocessor reference design as an example system for the multiprocessor integrated circuit. The implemented functional components of the modular multiprocessor reference design may be suitable for testing software for operation by the multiprocessor integrated circuit. Moreover, the modular multiprocessor reference design enables testing of interaction of functional components for providing the desired functionality of the received specification.

Abstract: An apparatus generally comprising a tuner circuit, an analog-to-digital circuit and a converter circuit. The tuner circuit may be configured to generate an intermediate frequency signal having a carrier signal at a first intermediate frequency in response to a first frequency conversion applied to a radio-frequency signal modulated by an analog television signal. The analog-to-digital circuit may be configured to generate a digital intermediate signal having the carrier signal at a second intermediate frequency in response to a digitization of the intermediate frequency signal. The converter circuit may be configured to generate a digital television signal representative of the analog television signal at a baseband frequency in response to a demodulation of the digital intermediate signal.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to present a first data signal and a first indicator signal in response to a first clock signal and an enable signal. The second circuit may be configured to present a second data signal and a second indicator signal in response to the first data signal, the first indicator signal and a second clock signal.

Abstract: A processor is disclosed including trace and profile logic for gathering and producing data corresponding to events occurring during instruction execution. In one embodiment, the trace and profile logic includes a serial queue for serializing data corresponding to a plurality of “discontinuity instructions” grouped together for simultaneous execution. A “discontinuity instruction” alters, or is executed as a result of an altering of, sequential instruction fetching.

Abstract: An apparatus comprising a plurality of first circuits and a second circuit. Each of the first circuits may be configured to translate attributes and data between one of a plurality of first predetermined formats and a second predetermined format. The second circuit may be configured to route the attributes and data in the second predetermined format from one of the first circuits to another of the first circuits.

Abstract: Systems and methods for expanding capacity of a storage system are provided. Data blocks of a capacity increasing disk are pre-configured with a first progress indicator used to determine correctly migrated data blocks. A migrator migrates groups of data blocks among present disk(s) and capacity increasing disk(s). Each group comprises a predetermined number of data blocks. An updater updates a second progress indicator of the second disk in response to completion of migration of each group. The migrator is adapted to generate the first progress indicator such that it may resume migration of groups of data blocks after a migration interruption according to the first and the second progress indicators.

Abstract: The present invention is directed to a system and method of providing an embedded input/output interface failover. An apparatus for providing an input/output interface with failover functionality between a host and a target may include a first data transfer route suitable for communicatively coupling the apparatus to a host system, a second data transfer route suitable for communicatively coupling the apparatus to a target, and a third data transfer route suitable for communicatively coupling the apparatus to the target. A memory suitable for storing electronic data is also included, the memory including a program of instructions. A controller is communicatively coupled to the first data transfer route, the second data transfer route, the third data transfer route and the memory.

Abstract: A system, method, and computer program product in a data processing system for increasing data storage performance. The data processing system includes multiple primary storage devices and a spare storage device. A logical volume definition is established that defines logical volumes utilizing the primary storage devices. A failure of one of the primary storage devices is detected. Data that was stored on the failed primary storage device at the time the failure was detected is constructed on the spare storage device. The spare storage device is then assigned in the logical volume definition such that the spare storage device becomes a primary storage device. The reference to the failed primary storage device is removed from the logical volume definition.

Abstract: Multiple matches of words in a content addressable memory are detected by identifying each match of the input word to a word in the memory, and generating a representation of a relationship OR(xi AND xj), where xi=x1, x2, . . . , xN-1, xj?xi+1, xi+2, . . . xN, and x1, x2, . . . , xN are the compare results of the individual words in the memory to the input word. A representation of at least one match is identified by generating a representation of a relationship x1 OR x2 OR x3 OR . . . OR xN. The apparatus comprises a hierarchy of logic that carries a general match representation indicating at least one match between the input word and all of the memory words, and a multiple-match representation indicating multiple matches between the input word and the words in the memory.

Abstract: The present invention is directed to a system and method for data verification in a RAID system. A method of verifying data in a RAID system may include reading a first item of data from a first data storage device and a second item of data from a second data storage device. The first item of data from the first storage device is compared with the second item of data from the second storage device. If the first item of data does not match the second item of data, a third item of data is read from a third data storage device. The third item of data is compared with the first item of data and the second item of data.

Abstract: A memory system for multiple processors includes a unified memory including a plurality of memory banks, and a memory controller coupled to the unified memory. The memory controller receives requests from the multiple processors, each of the requests including information of a memory address. The memory controller selects one of the memory banks by asserting a request signal only for a memory bank including the requested memory address, and provides the requesting processor with a requested memory operation on the selected memory bank.