Abstract: An apparatus for controlling the substrate temperature of a substrate during processing of the substrate at a process energy. A chuck temperature input receives temperature measurements from temperature sensors at a substrate chuck, and a temperature set point input receives temperature set points. The temperature set points define a range of temperatures within which the apparatus maintains the substrate temperature. A chuck temperature controller output sends control signals to a chuck temperature controller, which signals are operable to selectively increase and decrease the chuck temperature. A process energy output sends control signals that are operable to selectively increase and decrease the process energy during the processing of the substrate. A controller compares the temperature measurements received from the temperature sensors at the substrate chuck through the chuck temperature input to the temperature set points received through the temperature set point input.

Abstract: A self-aligning memory cell design is provided to allow testing of transistors in every cell of a memory circuit. A test array of these cells is fabricated with contact pads in each cell for specific components in the cell. Then, metal lines are provided to couple the contact pads in the test array. The whole test array is then probed via these metal lines. Tests may then be performed to detect random and systematic transistor degradation electrically for all cells in the circuit. Different components in the memory design may be tested by providing contact pads for the components of interest and providing metal lines coupling the contact pads.

Abstract: A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon germanium channel layer on the substrate. A gate insulation layer is formed on top of the strained silicon germanium channel layer, at a temperature that does not exceed about eight hundred centigrade. A gate electrode is formed on top of the gate insulation layer, and the gate electrode is patterned. A low dose drain dopant is impregnated into the substrate, and activated with a first laser anneal. A source-drain dopant is impregnated into the substrate, and activated with a second laser anneal. After the step of activating the low dose drain dopant with the first laser anneal, an insulating layer is formed around the gate electrode, at a temperature that does not exceed about eight hundred centigrade, and a spacer is formed around the gate electrode. The spacer is formed of a material that is reflective to the second laser anneal.

Abstract: Test structures are provided for accurately quantifying shared contact resistance. The test structures are built based upon an actual memory cell, which is self-aligning to allow shared contact chains through an array of test cells. A main array of test cells is built to provide a chain of shared contact resistance. Using the main array of test cells, a resistance in the shared contact chain may be measured. Supplemental arrays of test cells is built to provide a chain of poly side resistance, a chain of island side resistance, a chain of island connection line resistance, and a chain of poly connection resistance. A tester measures resistance using the test structures and uses the values to accurately determine shared contact resistance.

Abstract: An apparatus comprising an analog circuit, a first digital circuit, and a second digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The first digital circuit may be configured to generate (i) one or more data signals, (ii) a first strobe signal, and (iii) a second strobe signal in response to the plurality of samples, the plurality of phases, and a correction signal. The second digital circuit may be configured to generate the correction signal and a width signal in response to (i) the one or more data signals, (ii) the first strobe signal, and (iii) the second strobe signal.

Abstract: A shift register is provided to monitor the difference between the read and write pulses to an elasticity buffer. The shift register essentially eliminates the need for any math functions in the elasticity buffer management logic. The shift register is as wide as the elasticity buffer is deep. In other words, for every word in the elasticity buffer, the shift register has a corresponding bit. Each time a word is written into the elasticity buffer without a simultaneous corresponding read, a value of “1” is shifted from a first end into the shift register, indicating that a space has been taken in the elasticity buffer. For every word read out of the elasticity buffer without a simultaneous corresponding write, a value of “0” (zero) is shifted from a second end of the shift register, indicating that one more space is available.

Abstract: An embedded memory on an integrated circuit chip is capable of being isolated from other on chip and off chip circuitry during power failure modes on the integrated circuit chip. The embedded memory preferably has its own external power supply. When power on chip fails or falls below a threshold level, input to and output from the embedded memory is prohibited by CMOS isolation cells. The CMOS isolation cells are controlled by enable signals and the power level of other power supplies within the integrated circuit.

Abstract: A mode register is created during the design of a complex, multi-mode electronic circuit. The mode register may contain connections to various switches, clocks, multiplexers, or other portions of the circuit that may have settings necessary to operate the circuit in different modes. The mode register may be used during circuit simulation by setting the mode register to a certain setting when running a static timing analysis script or other type of circuit simulation. After the circuit design is completed and before manufacturing the circuit, the mode register is disabled or removed from the circuit.

Abstract: For use in a wide-issue pipelined processor, a mechanism for, and method of, reducing pipeline stalls between conditional branches and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a mispredict program counter (PC) generator that generates a mispredict PC value for each conditional branch instruction in a pipeline of the processor and (2) mispredict PC storage, coupled to the mispredict PC generator, that stores the mispredict PC value at least until a resolution of the conditional branch instruction occurs and makes the mispredict PC value available to a PC of the processor if the resolution results in a mispredict condition. The mispredict PC storage includes a mispredict PC queue and a number of staging registers wherein the mispredict PC queue has at least as many stages as the number of staging registers.

Abstract: A method and system for communicating across heterogeneous networks having components with dissimilar data structure definitions is disclosed in which determinations are made as to whether the sender is up-level or down-level and whether the up-level data structure size is greater or lesser than the down-level data structure size. According to these determinations, data fields for the decoded data structure may skip data or assign default values. The invention reduces upgrade costs and system down time.

Abstract: An integrated circuit (IC) and methods of manufacturing and operating ICs. In one embodiment, the IC includes: (1) a plurality of interchangeable hard macrocells, (2) at least one programmable logic block (PLB), (3) a bus intercoupling said plurality and said at least one programmable logic block and (4) a self-repair program, associated with said at least one programmable logic block, that causes said PLB to test at least some of said plurality and place at least a functioning one of said plurality into an operational status.

Abstract: A method, rules and directives engine, and a computer program product that simplifies the design of semiconductor products. Starting with an application set which is a partially manufactured semiconductor platform that is correct-by-construction, as a chip designer inserts her/his own designs into the platform, a system of rules and directives check each input to ensure that naming conventions are followed, that the input is compatible with all other components to which it is connected, than the input has the necessary and appropriate power, signals levels, clocks, memories. As a component is generated from a configurable transistor fabric that is part of the application set, the parameters of the configured component are inserted and checked for the power, signal, clocking, and memory compatibility, e.g., I/O buffers are verified for proper signal levels, differential signals, power plane compatibility, etc.

Abstract: A clock integration method, tool, and a computer program product that captures, creates, and seamlessly integrates a clock specification to achieve a correct-by-construction design flow of a semiconductor product, such as an ASIC, from a partially manufactured semiconductor platform. The clocking elements of the design flow are combined and displayed to a chip designer in a plurality of context-driven user interfaces and views. Within each view, the details of the clock specification are presented in the context of the information to guide a chip designer to make relevant and correct determinations, e.g., if the context is a high level overview of the logic of the intended semiconductor product, then only the high level parameters, such as source, frequency, path of the clocks signals through the high level modules, etc. are seen. When a chip designer wants more or less detailed information, she/he need only zoom in/zoom out through the plurality of views of the design flow.

Abstract: During the design of semiconductor products which incorporates a user specification and an application set, the application set being a partially manufactured semiconductor platform and its resources, a template engine is disclosed which uses a simplified computer language having a character whereby data used in commands identified by the character need only be input once, either by a user or by files, and that data, after it has been verified to be correct, is automatically allocated to one or more templates used to generate shells for the specification of a final semiconductor product. Data must be correct and compatible with other data before it can be used within the template engine and the generated shells; indeed the template engine cooperates with a plurality of rules and directives to verify the correctness of the data.

Abstract: A system for, and method of, reference-modeling a processor design. In one embodiment, the system includes: (1) an architecture database that contains specifications regarding the processor design that include: instruction set specifications, architectural resource specifications, pipeline specifications and connectivity specifications, (2) a simulation subsystem that draws selected portions of the specifications to simulate and test the processor design and (3) a documentation subsystem that draws other selected portions of the specifications to document and register-model the processor design, changes in the specifications being propagated to the architecture database.

Abstract: A self-timed scan circuit includes a multiplexer for selecting either a data input or a test input in response to an internal test enable signal and for generating a multiplexed output; a latch coupled to the multiplexer for generating a latched output in response to a next clock pulse; and a timing control circuit for generating the internal test enable signal in response to a global test enable signal wherein the internal test enable signal is set to logic one when the global test enable signal is set to logic one and wherein the internal test enable signal is set to logic zero in response to the next clock pulse.

Abstract: A method and control system for detecting harmonic oscillation in a chemical mechanical polishing process and reacting thereto, such as by taking steps to at least one of: 1) reduce or eliminate the harmonic oscillation; and 2) counter the noise which is associated with the harmonic oscillation. By reducing or eliminating harmonic oscillation, films with reduced structure strengths including low k dielectric films can be used. By countering the noise, the quality of the work environment is improved.

Abstract: A method of recovering from loading invalid data into a register within a pipelined processor. The method comprises the steps of (A) setting a register status for the register to an invalid state in response to loading invalid data into the register and (B) stalling the processor in response to an instruction requiring data buffered by the register and the register status being in the invalid state.

Abstract: A low-k interconnect dielectric layer is strengthened by forming pillars of hardened material in the low-k film. An E-beam source is used to expose a plurality of pillar locations. The locations are exposed with a predetermined power and exposure time to convert the low-k film in the selected locations to pillars having higher hardness and strength than the surrounding portions of the low-k film.

Abstract: A design and verification aide that can be used to produce BZ codes under static or dynamic process, voltage, temperature and external reference resistor (PVT and R) conditions for impedance controlled buffers or any other application using BZ codes. The simulation technique follows that of a flash ADC, and effectively replaces an awkward state-machine BZ controller with a subcircuit consisting of 5 BZREFN's, 5 BZREFP's, 10 HSPICE behavioral comparators, and the BZVREF. The resulting N- and P-codes may be adjusted by a parameterized dither count with minimum and maximum code values enforced by the model, and the comparators can be modified to model offset voltage.