Abstract: An audio/visual (A/V) device, such as a DVD player, assists a user in finding desired programming from among DVD programs, conventional broadcast television (TV) programs and World Wide Web transmitted programs. The programs contain close caption (CC) and A/V content. The A/V device captures and stores the CC and/or A/V content either for current or later manual use by the user or concurrent automatic searching for desired program content or information. Text-based searching is performed on the CC content for a match with user-specified textual search criteria. The audio context is searched for either a change that indicates a change in programming or a match with user-specified audio search criteria. A video still image is captured from the video content for manual viewing or automatic comparison to a desired image. The A/V device also presents the information, including the A/V content, captured CC content and search results, on either a conventional TV or higher resolution progressive monitor.

Abstract: A method and system for selectively interconnecting two SCSI host buses where each SCSI host bus includes a host device and multiple addressable SCSI target devices, each SCSI target device having a multibit SCSI ID associated therewith. A SCSI cross-link repeater is interposed between the two SCSI host buses and selectively enabled. Each time the SCSI cross-link repeater is enabled, the repeater enable signal is utilized to automatically alter the most significant bit of the multibit SCSI ID associated with each SCSI target device on the second SCSI host bus, such that those SCSI target devices do not duplicate the SCSI IDs of the SCSI target devices on the first SCSI host bus. Disabling the SCSI cross-link repeater automatically resets the most significant bit of the multibit SCSI IDs, restoring the original SCSI IDs for those devices.

Abstract: A method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description. Through analyzing the dependency relationship among operators used to define the logic function, the present invention may simplify the functional steps used in the high-level description to define the logic function and thus create a logic circuit with an optimized number of AND/OR switches.

Abstract: A dedicated hardware CRC computation engine is provided to assure the integrity of data transferred between the system memory and storage devices. The CRC computation engine provides CRC calculation “on-the-fly” for the protection of data transferred to and from the system memory without software overhead. The computation of CRC values and optional checking against previously calculated CRC values is selected through the use of an address-mapping scheme. This CRC protection scheme requires a small amount of initial software overhead to allocate the data, CRC value, and CRC error regions of the system memory. After the CRC protection scheme is initialized, all CRC operations are transparent to the executing software.

Abstract: An apparatus comprising a counter circuit, a first register circuit, a second register circuit and an output circuit. The counter circuit may be configured to generate a count signal in response to a data input signal and a first clock signal operating in a first clock domain. The first register circuit may be configured to generate a first control signal in response to the count signal. The second register circuit may be configured to generate a second control signal in response to the data input signal. The output circuit may be configured to generate a data output signal operating in a second clock domain in response to the first control signal, the second control signal, the count signal, and a second clock signal.

Abstract: The present invention may provide a digital memory circuit comprising a plurality of multi-bit registers, a memory circuit interface, and a logic circuit. The memory circuit interface may be configured to access a selected one of the registers. The logic circuit may be coupled to the plurality of multi-bit registers and responsive to data received through the interface for selectively writing a predetermined logic state to at least one first bit of the selected register while leaving at least one second bit in the selected register with an unmodified state.

Abstract: The invention relates to an integrated circuit including a hard-core and a peripheral circuit. The hard-core and the peripheral circuit each include respective registers, which are couplable for scan chain testing by respective scan chain paths within the core and within the peripheral circuit. In order to avoid timing problems between the two scan chain paths, a lock-up latch is provided within the hard-core. The lock-up latch has an input coupled to the last register in the scan chain path within the hard-core, and an output coupled to the first register in the scan chain path in the peripheral circuit. The lock-up latch forms part of the hard-core and is clocked by the same clock signal as the last register in the hard-core scan chain path.

Abstract: An embodiment of the present invention provides a novel method which makes LVR to HVR registration possible by wrapping the X and Y scribes around each instance of each layer on both the LVR and HVR reticles; standard HVR reticles and LVR reticles will not align to one another due to registration and electrical test structures in the scribe being in different locations. Another embodiment of the present invention addresses the loss of die per wafer due to increased sribe area when using LVR and HVR reticles in the same set.

Abstract: A method for optimal placement of cells on a surface of an integrated circuit, comprising the steps of comparing a placement of cells to predetermined cost criteria and moving cells to alternate locations on the surface if necessary to satisfy the cost criteria. The cost criteria include a timing criterion based upon interconnect delay, where interconnect delay is modeled as a RC tree expressed as a function of pin-to-pin distance. The method accounts for driver to sink interconnect delay at the placement level, a novel aspect resulting from use of the RC tree model, which maximally utilizes available net information to produce an optimal timing estimate. Preferred versions utilize a RC tree interconnect delay model that is consistent with timing models used at design levels above placement, such as synthesis, and below placement, such as routing. Additionally, preferred versions can utilize either a constructive placement or iterative improvement placement method.

Abstract: A command processor of an integrated circuit design suite has a graphical user interface and a command interpreter for interpreting user commands. The graphical user interface is specified entirely by a user at run time. One or more design tools corresponding to processes within an integrated circuit design process operate under the control of the command processor and within the graphical user interface.

Abstract: An IC layout containing megacells placed in violation of design rules is corrected to remove design rule violations while maintaining the original placement as near as practical. The sizes of at least some of the megacells are inflated. The megacells are placed and moved in a footprint of the circuit in a manner to reduce placement complexity. The placement of the megacells is permuted to reduce placement complexity. Additional movements are be applied to the permuted placement to further reduce placement complexity.

Abstract: An integrated circuit is provided, which includes a phase-locked loop (PLL) that is fabricated on the integrated circuit and has a selectable loop filter capacitance and a selectable output frequency range.

Abstract: A system and method for evaluating multiple corner case static timing analyses. For each node within the analysis, the variability and margin of the node is used to create a risk factor that is used to identify nodes for further analysis. In some cases, a subset of nodes may be selected for static timing analysis with several additional corner cases. The variability of the node may be determined by the difference between the maximum and minimum value of the node between corner case analyses. The margin may be determined by the difference between the actual timing and the required timing. Various ratios using variability and margin may be used to identify those nodes on which to perform further analysis.

Abstract: A flip chip substrate is provided, which includes a plurality of conductive layers, including a top layer and a bottom layer. A first plurality of contacts, including first and second contacts corresponding to a differential signal pair, are arranged on the top layer within a die bonding area. A second plurality of contacts, including third and fourth contacts corresponding to the differential signal pair, are arranged on the bottom layer. First and second traces are routed between the first and third contacts and between the second and fourth contacts, respectively, wherein the second trace is routed out of the die bonding area on a different layer than the first trace. The traces are routed in a manner that reduces the length difference between the traces.

Abstract: A method and system is disclosed to improve the turnaround time to provide adequate time to meet project schedules in the event that adjustments or modifications to the design are necessary. A method for improving a turnaround time for design verification of a process database representing a semiconductor design includes the steps of (a) deriving a timing database and a (DNE) database from the process database; (b) performing, using the timing database, one or more design changes and one or more timing verifications and corrections to generate a modified timing database; (c) initiating, using the process database, physical validation of the semiconductor design prior to completion of step (b) to generate a modified DNE database; (d) merging the modified timing database with the modified DNE database to form a modified process database; and (e) performing, using the modified process database, one or more design verification checks of the semiconductor design.

Abstract: Disclosed is a method for converting a SPICE format circuit description to a standard cell HDL netlist, such as Verilog, allowing simulation and verification in HDL format. SPICE elements may be converted to circuit functions and corresponding standard cells are then selected. The SPICE netlist is employed to define timing paths. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of the SPICE simulation. The present invention may also employ SPICE to Verilog conversion wherein a SPICE netlist is converted to a Verilog standard cell netlist. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells in the Verilog netlist and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of SPICE simulations.

Abstract: A method and apparatus control switching noise in a digital-to-analog interface in a mixed-signal circuit. The digital-to-analog interface includes a first plurality (K) of switching elements and a second plurality (M) of dummy switching elements, the second plurality (M) being smaller than the first plurality (K). The switching noise control includes (a) receiving a digital data signal, (b) determining a number (N) of the switching elements to be switched for the digital data signal, and (c) switching the second plurality (M) less the number (N) of the dummy switching elements simultaneously with switching the number (N) of the switching elements.

Abstract: A method and system for performing optical proximity correction (OPC) on an integrated circuit (IC) chip design is disclosed. The system and method of the present invention includes exploding calls on an element list to generate an expanded element list, defining a local cover area for each call on the expanded element list, classifying congruent local cover areas into corresponding groups, and performing an OPC procedure for one local cover area in each group By defining the local cover area for each call and grouping congruent local cover areas, only one OPC procedure (e.g., evaluation and correction) needs to be performed per group of congruent local cover areas. The amount of data to be evaluated and the number of corrections performed is greatly reduced because OPC is not performed on repetitive portions of the IC chip design, thereby resulting in significant savings in computing resources and time.

Abstract: On-chip absolute value measurement circuit and an on-chip capacitor mismatch value measurement circuits are provided. The absolute value measurement circuit begins charging a capacitor. When the voltage across the capacitor reaches a first threshold, the absolute value measurement circuit starts a counter. When the voltage across the capacitor reaches a second threshold, the counter stops. The counter value is provided as digital output. A computer device reads the digital output and calculates the absolute value of the capacitor based on the counter value. The mismatch measurement circuit repeatedly charges an evaluation capacitor and transfers the charge from the evaluation capacitor to an integrating capacitor. For each transfer of charge, a counter is incremented until the voltage across the integrating capacitor reaches a threshold voltage. The counter value is provided as digital output. This process is repeated for each evaluation capacitor on the chip.

Abstract: A system and method are presented for neutralizing the electric charge binding a semiconductor wafer to an electrostatic chuck. When processing of a semiconductor wafer has been completed, lifter pins, driven by solenoids or pistons, are provided within the chuck to remove the wafer. However, if the electrostatic force has not been completely dissipated, the pins may have to push very hard against the wafer to dislodge it. When this occurs, the wafer may be violently displaced from the chuck, resulting in misplacement of the wafer, or even damage. A system and method are disclosed herein for completely neutralizing the electrostatic charge before removal of the wafer is attempted. Neutralization is detected as the point at which the electrostatic force opposing the lifting mechanism reaches a minimum.