Abstract: An integrated circuit having a gate region, a source drain region, and an electrically nonconductive spacer separating the gate region and the source drain region. A local interconnect electrically connects the gate region to the source drain region across the electrically nonconductive spacer. The local interconnect is formed of a semiconducting material reacted with a metal. The local interconnect may be formed by implanting a precursor species into the electrically nonconductive spacer. A metal layer is deposited over at least the electrically nonconductive spacer, and the integrated circuit is heated to form an electrically conductive local interconnect from the metal layer and the precursor species implanted in the electrically nonconductive spacer.

Abstract: A method of forming a photo-resist image on a substrate, such as a conductive film. The method provides that a photo-resist image is printed directly onto the conductive film, such as by using an ink jet printer. Specifically, a CAD image may be sent from a computer to the ink jet printer, and the ink jet printer may use the CAD image to print the photo-resist image. The method may provide that a copper film is applied to a dielectric substrate, and then the photo-resist image is printed directly onto the copper film. Then, at least a portion of the copper film is removed, such as by etching, and at least a portion of the photo-resist image which has been printed on the copper film is removed, such as by etching. By printing the photo-resist image directly onto the copper film, it is not necessary to perform steps such as: applying a mask, exposing to UV light, and developing.

Abstract: A method and apparatus in a data processing system for mimicking a device attached to a bus. Signaling is detected on the bus indicating a request to access the device. The bus is then monitored for a response by the device. If a selected period of time passes without a response being made by the device, a response suitable to indicate the presence of the device is sent onto the bus.

Abstract: A standardized silicon platform chip has a substrate surface with an array of unconnected transistors that surround islands. The islands have circuit elements that are interconnectable within each island to form a plurality of varied circuit functions for each of the islands. The varied circuit functions include both application functions and clock functions. Interconnect layers are deposited over the substrate surface to interconnect the circuit elements within each island to complete the varied circuit functions. The varied circuit functions include varied levels of integration including at least gates, flip-flops, clock trees, and oscillators. The varied circuit functions are custom connectable to the array of unconnected transistors to form standard clock resources for the standardized silicon platform chip.

Abstract: The present invention is directed to a method and an apparatus for automatically configuring and/or inserting chip resources for manufacturing tests. A maximum test configuration (“test backplane”) for all IP blocks is created and loaded into a tool suite. When a user issues a request to consume some IP blocks, the request may be checked for legality within the “test backplane”. If a test resource (IP block) is not available for activation, then either the test resource may not be activated or the conflicting resource problem must be resolved so that the test resource may be activated. This may avoid late design surprises. The resources on the platform may already have test structures associated with them. All of these test structures may be associated with the “test backplane”. These pre-exiting test structures may then be connected.

Abstract: A method of characterizing a total width and an overall effective length for a bent gate. The bent gate is divided into logical portions, and each of the logical portions is designated as one of a bent portion, a corner portion, and a straight portion. A corner portion gate width and a corner portion effective length are computed for each of the logical portions designated as a corner portion. Similarly, a bent portion gate width and a bent portion effective length are computed for each of the logical portions designated as a bent portion. Likewise, a straight portion gate width and a straight portion effective length are computed for each of the logical portions designated as a straight portion. The total width of the bent gate is computed from the corner portion gate width, the bent portion gate width, and the straight portion gate width.

Abstract: A resistance measurement circuit includes a plurality of current sources, a plurality of resistor strings and a comparator. Each resistor string is coupled in series with a respective one of the current sources and includes a plurality of nodes with different resistances relative to a reference node. Each node in each resistor string has a different resistance relative to the reference node than corresponding nodes in the other resistor strings. The comparator has a first comparison input coupled to a reference voltage and a second comparison input selectively coupled to the plurality of nodes in each resistor string.

Abstract: A receiver with initial offset for biased idle transmission line suitable for providing a programmable amount of initial offset. The receiver comprises a standard differential receiver and one or more initial offset modules. Each initial offset module includes a transistor and two or more switches, which control the amount of offset to the differential receiver. A first switch receives a digital signal, which programs the amount of offset and a complementary digital signal is sent to a second switch to control the addition of the selected initial offset module(s).

Abstract: A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized data frame. Both the configuration data and a frame clock may be propagated through the plural stages from a master switch. First and last stages of the digital cross connect may be implemented on common chips having two framing time bases. Data may be aligned to a global frame clock and interchanged using a single random access memory in a time slot interchanger. The write address to the random access memory is generated from a local frame counter keyed to the input data frame while a read address is transformed from a global frame counter.

Abstract: A memory having built-in self repair with row shifting is provided. The rows in the memory are divided into smaller row groups and a bad row group is repaired with a redundant row group. Each row group receives a row select signal, which is fed into a shift circuit for the row group and a shift circuit for an adjacent row group. A shift circuit is provided for the redundant row group and the shift circuit for the redundant row group receives the row select signal for only the adjacent row group. If a bad row group is detected, then starting with the row group furthest from the redundant row group, the shift circuit for each row group before the bad row group is deactivated. The row group select signal and word line signal for the bad row group are disabled. The shift circuit for the bad row group and the shift circuit for each row group after the bad row group are activated. Therefore, the bad row group is disabled and the redundant row group fills the void.

Abstract: An apparatus for monitoring the condition of a lubricating medium includes a UV light source, a UV receiver, a processor electrically coupled to both the UV light source and the UV receiver, and a memory device electrically coupled to the processor. The memory device has stored therein a plurality of instructions which, when executed by the processor, cause the processor to (a) communicate with the UV light source and the UV receiver so as to expose a sample of the lubricating medium to the UV light and generate a UV spectrum of the sample in response thereto, and (b) compare the UV spectrum of the sample to a model spectrum and generate a control signal if the UV spectrum of the sample has a predetermined relationship to the model spectrum.

Abstract: A decoder generally comprising a branch metrics circuit and a state metrics circuit. The branch metrics circuit may be configured to generate a plurality of branch metric signals. The state metrics circuit may be configured to (i) add the branch metric signals to a plurality of state metric signals to generate a plurality of intermediate signals, (ii) determine a next state metric signal to the state metric signals, (iii) determine a normalization signal in response to the intermediate signals, and (iv) normalize the state metric signals in response to the normalization signal.

Abstract: A line interface couples signals between a data transceiver and a transmission line having a load impedance Z. The line interface includes a transformer, a driver circuit for supplying a transmit signal from the data transceiver to the transformer, and a receiver circuit for receiving a receive signal from the transformer. The transformer includes a first port coupled to the transmission line, a second port coupled to the driver circuit, a third port coupled to the receiver circuit, a first winding part having a turns ratio of 1: n, where n>1, for coupling the transmit signal from the second port to the first port, and a second winding part having a turns ratio of 1: m, where m<n, for coupling the receive signal from the first port to the third port.

Abstract: An apparatus comprising a controller circuit and a BISR assembly circuit. The controller circuit may be configured to present one or more control signals. The control signals may be configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation. The BISR assembly circuit generally comprises one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution during the BIST and BISR operations. The memory blocks may be remapped in response to the count values during one or more of the BISR operations.

Abstract: For use in a processor having separate instruction and data buses, separate instruction and data memories and separate instruction and data units, a mechanism for, and method of, supporting self-modifying code and a digital signal processor incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a crosstie bus coupling the instruction bus and the data unit and (2) a request arbiter, coupled between the instruction and data units, that arbitrates requests therefrom for access to the instruction memory.

Abstract: Application of an extremely low K material by the application of a laminate onto a wafer. The laminate preferably contains alternating layers of low K material and etch stop layers, and could be applied by rolling the laminate onto the wafer. An anneal process can be utilized to bond the film to the wafer. Conventional photo masking and etching techniques are then used to open vias and line areas in the film, and to deposit the next copper layer on the wafer. Electro polishing can be used to planarize or remove residual copper. Thereafter, an etch step can be performed to remove the excess material between the copper lines to leave an ultra low K region between the copper lines. The next layer of low K film can then be deposited, and the process repeated for all subsequent metal layering.

Abstract: A phase-locked loop within an integrated circuit assembly is provided. The phase-locked loop includes a plurality of subcells of semiconductor devices arranged in a base layer pattern on base layers of the integrated circuit assembly. One or more metal layers are formed over and interconnect the plurality of semiconductor devices in a metallization pattern. The phase-locked loop has an output frequency range that is changeable with a change to the metallization pattern without a corresponding change to the base layer pattern.

Abstract: A method and system is provided for automatically calibrating a masking process simulator using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected. Data defining the calibration mask and at least one of the process parameters are input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The alim image and the detected edges of the digital image are then overlaid, and a distance between contours of the pattern in the alim image and the detected edges is measured. One or more mathematical algorithms are used to iteratively change the values of the processing parameters until a set of processing parameter values are found that produces a minimum distance between the contours of the pattern in the alim image and the detected edges.

Abstract: Methods and associated structure for providing a substitute, predetermined, fixed length when transferring burst transactions from one device to another through a bridge device where the burst transaction has an indefinite length specified. In one exemplary preferred embodiment, an AMBA AHB bus bridge slave device recognizes initiation of burst transactions of a indefinite length and translates the indefinite length burst transactions on the first bus into appropriate bus transactions for application to a second bus or device having a predetermined fixed length for the transferred the burst transactions. In a second embodiment, a slave device acting as a bridge receives a burst of indefinite length and translates the bus request into one with a predetermined fixed length for application to a device controller.

Abstract: Integrated circuits are designed having optimal signal timing between and among cells. A set of identities are generated corresponding to logic operations and to library cells in technology basis. A resynthesis window is created for the identities having less than a predetermined depth of critical variables. Logic equations of the resynthesis window are transformed using the identities, and the resynthesized window area is optimized.