Abstract: The present invention provides systems and methods for copying and/or transferring stored data of one storage volume of a storage system to another storage volume while enabling requests to the storage volumes. The systems and methods may be particularly useful in RAID storage systems. One system includes a detector configured for detecting an amount of the stored data copied from the one storage volume to the other storage volume based on a boundary marker of the storage volumes. The boundary marker may indicate an amount of the stored data copied from the one storage volume to the other storage volume. A processor is communicatively connected to the detector for processing requests to the storage volumes according to rules based on the boundary marker. A file generator may generate a log file of the requests. The log file may be stored in the other storage volume thereby minimizing a need for external storage devices.

Abstract: Systems and methods for transferring data. A circuit transfers information between two buses using different signal voltage levels and multiplexes signals applied to the second bus over multiple devices coupled thereto. The data on a first data bus is transferred at a first voltage level and the data on a second data bus is transferred at a second voltage level. For example, the first data bus may transfer data at 3.3V and the second data bus may transfer data at 5V. A logic device (e.g., a CPLD) is connected between the first and the second data buses for transferring the data between the first and second voltage levels. The logic device is also configured for multiplexing the data with the second voltage level between first and second devices (e.g., one or more LEDs and/or NVSRAMs) connected to the second data bus.

Abstract: An apparatus for generating graphics is connectable in a computer system between a system processor and a system memory by way of a data bus. The apparatus comprises two registers for the storage of X and Y coordinates respectively of a single pixel. The coordinates are applied to an address conversion calculation unit for calculating a linear memory address corresponding to the pixel coordinates and the data representative of the pixel is stored in the system memory at the calculated address. The two registers are memory mapped to appear at two or more locations in memory such that operation of the apparatus is dependent on the memory location used by each register. The apparatus carries out many of the repetitive operations required in the generation of graphics.

Abstract: In a Framed Packet Bus (FPB) serial bus, an improved protocol and circuit layout for communication between devices grounded in the same chassis or chip. The improved protocol eliminates the requirement that bits have DC balance in their HIGH and LOW voltage levels. Consequently, bus overhead is reduced over prior techniques. In one example, data capacity utilization was increased from 80% to 95% and bus overhead was reduced from 20% to 5%. As a result of increased capacity, more packets of data may be carried across the serial bus, and any leftover bits within the frame cycle and in subsequent cycles may carry error detection information or be utilized as a control for the bus. In one preferred embodiment, the FPB serial bus configuration consists of sixteen serial lines arranged in parallel.

Abstract: A method for optimizing an algorithm specified for implementation on an integrated circuit for a specified application. The algorithm is analyzed with respect to its performance, and estimates of implementation area and speed are calculated. Specifically, the degrees of freedom for the algorithm alternations under specific targeted implementation objective functions and constraints are identified. The algorithm solution space is then searched to identify the algorithm structure that is best suited for the specified design goals and constraints. Algorithm parameters which satisfy performance metrics and can be implemented with minimum silicon area are identified.

Abstract: An apparatus comprising a first plurality of parallel switches and a second plurality of parallel switches. The first plurality of parallel switches may be configured to control a voltage on a first output pin. The second plurality of parallel switches may be configured to control a voltage on a second output pin. The first and second pluralities of parallel switches may be configured to provide rise time control of a differential waveform and be driven by a phased data signal.

Abstract: A method and system for automatically instantiating built-in-system test (BIST) modules in memory designs is disclosed. The method and system include providing a server over a network that integrates a set of design tools, including an automated front-end software process and an automated back-end software process. According to the method and system, a user may access the server over the network and enter a request for a memory design. The front-end software process is then executed to automatically generate a netlist of a BIST from the user request. Thereafter, the back-end software process is executed to automatically generate a placement and route view of the BIST.

Abstract: A method of inspecting a subject integrated circuit. A set of historical integrated circuits is inspected to detect defects and produce historical data. Features of the historical integrated circuits that have an occurrence of defects that is greater than a given limit are designated as high risk features, based on the historical data. Locations of the high risk features are identified on the subject integrated circuit. The locations of the high risk features are input into an inspection tool, and the locations of the high risk features on the integrated circuit are inspected to at least one of detect defects and measure critical dimensions, and produce subject data.

Abstract: A system for thinning a layer on a substrate without damaging a delicate underlying layer in the substrate. The system includes means for mechanically eroding the layer on the substrate, and means for electropolishing the layer on the substrate. In this manner, portions of the layer that cannot be removed by electropolishing can be removed by the mechanical erosion. However, electropolishing can preferentially be used on some portions of the layer so that unnecessary mechanical stresses can be avoided. Thus, the system imparts less mechanical stress to the substrate during the removal of the layer, and the delicate underlying layer receives less damage during the process, and preferably no damage whatsoever.

Abstract: A high availability storage system is provided in a server. The server includes a plurality of storage controllers. The storage controllers may be connected to storage enclosures that house the physical devices. If one controller fails, the second controller assumes command of the drive array handled by the failed controller with no interruption of server operation or loss of data. The controllers are connected to the physical drives via a channel or bus, such as a small computer systems interface bus. When two or more teaming controllers are active, the channel or bus may be split to increase throughput. A team driver is provided to direct and redirect requests to the appropriate controllers. The team drive may detect a failed controller, rejoin the bus, and assign control of all logical or physical drives to the remaining active controller. The team driver may also detect a new controller being added to the system, slit the bus, and divide the logical drives between the teaming controllers.

Abstract: A system and method for protecting the values stored in a BISR repair block and, optionally, debugging the BISR repair logic without altering normal test flow is implemented by a circuit including a plurality of soft latches within the BISR repair block, the soft latches being coupled together to form a BISR scan chain for holding BISR repair information. A chip level scan enable signal and a scan hold control signal cooperate to control connection of the BISR scan chain to other scan chains during a scan test, so that the BSR repair information is held within the soft latches. A diagnose enable signal cooperating with the chip level scan enable signal and the scan hold control signal for enabling debugging of logic connecting the BISR scan chains.

Abstract: A controller for repairing a redundant memory circuit includes a fault storage matrix for mapping a repair solution, a plurality of registers for storing row and column coordinates of the repair solution, and a repair solution calculator coupled to the plurality of registers and the fault storage matrix for receiving an x-coordinate and a y-coordinate of a defective memory cell in the redundant memory circuit and for determining whether a repair solution may be found from the fault storage matrix.

Abstract: A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels.

Abstract: A technique for detection and bypass of unnecessary modulation/demodulation and compression/decompression of Group 3 fax, in a telecommunication network having more than one pair, or “tandem,” Group 3 fax relay gateways. Detection and the effective removal of a Group 3 fax tandem reduces end-to-end processing delays of the facsimile signal, and improves performance of the Group 3 fax communication. The invention uses frequencies normally used for voice information (such as V.21 channel 1 frequencies) to detect tandem fax relay gateways and effectively remove unnecessary relay gateways.

Abstract: An apparatus comprising a sampler circuit and a filter circuit. The sampler circuit may be configured to generate a digital signal in response to a pre-amplified signal. The filter circuit may be configured to generate a track ID signal in response to the digital signal. The filter circuit may also be configured to (i) improve or increase signal-to-noise ratio (SNR) and (ii) reject DC offset errors.

Abstract: A method for compressing/decompressing data, comprising the steps of translating a first representation of data to a second representation of the data and translating the second representation of the data to a third representation of the data.

Abstract: A semiconductor wafer is placed into a probe fixture with a front side of the wafer facing up. Power and signal probes are then placed on an integrated circuit (IC) formed on the front side of the wafer. The probe fixture is retained at a test station either in a upright or an inverted position for testing and optical failure analysis. The probe fixture includes a position adjustment mechanism to locate the entire probe above the wafer and to more precisely position a tip of the probe on the IC. Optical failure analysis techniques are performed on the front side or the back side of the wafer while the wafer is retained in the test fixture and the probes are connected to the IC.

Abstract: A method of routing a metal layer trace in an integrated circuit die includes steps of: (a) receiving as input a netlist of an integrated circuit die; (b) selecting a redistribution layer trace from the netlist for routing the redistribution layer trace between an I/O pad of the integrated circuit die and a termination point; (c) comparing a trace width of the redistribution layer trace with a maximum trace width limit; and (d) if the trace width of the redistribution layer trace exceeds the maximum trace width limit, then routing the redistribution layer trace as a plurality of separate parallel traces each having a trace width that is less than the selected maximum trace width limit.

Abstract: A core voltage to input output voltage level shifter of the type that uses a reference voltage source to generate a reference voltage to limit a drain voltage on at least one voltage sensitive node connected to a voltage sensitive switching device, that resides on a high voltage domain. A feed back line runs from the voltage sensitive node to the reference voltage source. A feed back structure varies the reference voltage in response to the drain voltage on the at least one voltage sensitive node, and thereby maintains the drain voltage at a substantially constant desired value.

Abstract: Systems and methods for testing data lines to determine signal degradation in the data lines. A system includes a signal generator for generating a test pattern and for transferring the test pattern through the data lines. The system also includes an analyzer communicatively connected to the data lines to determine degradation of the test pattern in the data lines. The signal generator generates and transfers a first test pattern through the data lines. The first test pattern includes a first portion having a first polarity and a second portion having a second polarity. The signal generator then generates and transfers a second test pattern through the data lines in response to transferring the first test pattern. The test patterns may be repeated one or more times to determine cross talk caused by inductive coupling between data lines and additive reflections.