Abstract: Rapid Thermal Processing of a semiconductor wafer is performed by scanning a laser beam across a silicon dioxide film in contact with a surface of the wafer. The silicon dioxide film absorbs the energy from the laser beam and converts the energy to heat. The heat, in turn, is transferred to the wafer. Temperature feedback can be obtained to increase control and uniformity of temperatures across the wafer.

Abstract: A surface-mount ball-grid array package is provided for an integrated circuit assembly. The ball-grid array package has a circuit chip recess through which vias extend to open on a bottom surface of the package. A peripheral portion of the package is defined around the vias formed in the recess, and an integrated circuit die is seated within this peripheral portion. During manufacture, the package is held on a vacuum chuck by applying vacuum to the peripheral portion of the package. An adhesive material is placed in the recess to extend partially through the vias. The circuit chip is thereafter disposed in the recess on the adhesive material to complete the fabrication process. Ambient air is communicated to the vias on the bottom surface of the package to prevent the adhesive from being pulled through the vias by the applied vacuum.

Abstract: A method of cell placement for an integrated circuit chip includes performing a contraction operation by which at least some of the cells are relocated to new positions that provide lower interconnect wirelength. For each cell, the centroid of the net of cells to which the cell is connected is computed. The cell is then moved toward the centroid by a distance that is equal to the distance from the current position of the cell to the centroid multiplied by a "chaos" factor. This process continues until a specific energy condition is met; then the `expansion` mode is entered. An expansion operation is then performed by which the net force exerted on each cell by other cells in the placement and a resulting altered velocity of the cell are calculated, and a new cell position is calculated based on the altered velocity over an incremental length of time. The system stays in expansion mode until another energy criterion is met.

Abstract: Electronic systems utilizing a plurality of integrated circuit packages having at least some large gaps between edges of a semiconductor die and the inner ends of package conductors defining a die-receiving area, one or more bond wire support structure are disposed in the gap, thereby causing a long bond wire to behave as two or more shorter bond wires. The bond wires are tacked to a top surface of the support structure by various alternative means. Alternatively, a "jumper" structure having conductive traces of graduated length can be disposed in the die-receiving area between the die and the edges of the die-receiving area, providing an intermediate connection between the die and the leads of the package, thereby permitting short bond wires to be used in lieu of long bond wires.

Abstract: A method of making a surface-mount technology plastic-package ball-grid array integrated circuit assembly. According to the method, a surface-mount ball-grid array package is provided for an integrated circuit assembly. The array package has a circuit chip recess through which vias extend, opening on a bottom surface of the array package. A peripheral portion of the array package is defined around the vias formed in the recess. The array package is held on a vacuum chuck by applying vacuum to the peripheral portion of package. An adhesive material is then placed in the recess to extend partially through the vias. A circuit chip is finally disposed in the recess on the adhesive material to complete the fabrication process. Substantially ambient pressure is communicated to the vias on the bottom surface of the array package to prevent the adhesive from being pulled through the vias by the applied vacuum.

Abstract: A method and circuit are disclosed for changing the output impedance of an impedance controlled buffer from an initial impedance to a final impedance, while minimizing data transmission errors. The buffer has a plurality of impedance control inputs, with each of the plurality of impedance control inputs receiving a corresponding one of a plurality of bits of a binary coded impedance control signal. The output impedance of the buffer is controlled as a function of a value of the impedance control signal. First, the value of the impedance control signal is changed from an initial value corresponding to the initial output impedance to an intermediate value corresponding to an intermediate output impedance which is less than the initial output impedance. Next, the intermediate value of the impedance control signal is changed to a final value corresponding to the final output impedance.

Abstract: A high speed capture latch includes differential data inputs, a latch clock input, a boost clock input, a current steering circuit, a switched current source, a latch element and first and second boost current sources. The current steering circuit has first and second differential control terminals which are coupled to the differential data inputs and control current through first and second current paths, respectively. The switched current source is coupled between the current steering circuit and a first voltage supply terminal and has a control terminal coupled to the latch clock input. The latch element is coupled between a second voltage supply terminal and the current steering circuit and provides a latch output. The first boost current source is coupled to the first current path between the latch element and the current steering circuit and has a control terminal coupled to the boost clock input.

Abstract: A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit on a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.

Abstract: A multiple match detection circuit including an array of N and P-channel pull-up and pull-down devices receiving a corresponding array of hit line signals for developing complementary bit line signals, which are provided to the respective inputs of a differential comparator. Respective buffers drive the bit line signals to a maximum voltage differential in normal mode. For each hit line asserted, the pull-up and pull-down devices modify the voltage of the corresponding bit line voltage between the bit lines by an incremental amount, thereby decreasing the differential. Any single hit line does not cause enough of a voltage change to reverse the polarity of the differential voltage between the bit lines.

Abstract: Electronic systems using certain non-square dies, such as triangular dies, greatly elongated rectangular dies, parallelogram dies, trapezoidal, and the like, are able to be laid out in the area of a circular semiconductor wafer more "efficiently" than square dies. Further, a peripheral area of these certain non-square dies is advantageously increased relative to the area contained within the peripheral area, to accommodate increased I/O connections to the active elements of the die.

Abstract: In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement.

Abstract: A process for lowering the dielectric constant of a layer on a semiconductor wafer is described. The presence of the fullerene in the composite layer changes its dielectric constant. The process forms, on the wafer, a composite layer comprising matrix-forming material and a fullerene. The fullerene may be removed from the composite layer to leave an open porous layer. Removing the fullerene may be accomplished, for example, by contacting the composite layer with a liquid which is a solvent for the fullerene but not for the insulation material or by oxidizing the fullerene. The processes and insulation layers described are particularly useful for integrated circuits.

Abstract: A greater lead count for a given die area can be achieved with "certain non-square" geometries formed by the inner ends of conductive lines. These include various triangular configurations, as well as "greatly elongated" rectangular, parallelogram and trapezoidal configurations. The conductive lines may be leads of a lead frame, leads on a tape-based package, or traces on ceramic or PCB-substrate packages. The package body may be formed to have a shape similar to that of the die receiving area, and may also be provided with external pins, ball bumps or leads. A number of these "certain non-square" packages may be assembled in an electronic system on a mother board. Unpackaged "certain non-square" dies may be connected to the ends of traces on a substrate, and encapsulated to form a multi-chip module.

Abstract: Substrates having a wide range of thickness, and intended to be overmolded with a plastic package body, are accommodated in a common mold. The top surface of the substrate is provided with a dam structure, which may be formed as an additional layer on the substrate, and which is preferably in the form of a square ring. A groove (channel) is machined (e.g., by routing) into the surface of the dam structure. The top mold half, having a cavity for forming the package body, is provided with a sealing structure at the periphery of the cavity. The sealing structure has a ridge fitting into the channel of the dam structure. The depth of the groove in the dam structure is readily adjusted to ensure uniform clamping pressure of the top mold half on the substrate, so that liquid molding compound is contained within the cavity and so that undue pressure is not exerted on the substrate.

Abstract: In a method and apparatus for selective convolutional interleaving or de-interleaving of symbols or data bits, a plurality of segments are defined in random access memory, with each segment including a different number of locations for storing symbols. Previously stored symbols are sequentially read out of current locations in the segments respectively, and new symbols are read into the current locations. Next locations in the segments are redesignated as current locations respectively, and the operation is repeated until all of the symbols have been interleaved or de-interleaved. The first location in each segment is designated by a respective segment pointer. The current and next locations are designated as relative offset pointers from the segment pointers, and these locations are incremented by incrementing the offset pointers. Interleaving or de-interleaving operation is determined by the direction in which the segments are sequentially selected for the read/write operations.

Abstract: A traffic control system includes a traffic planner that communicates with a cellular telephone system to help manage the flow of traffic, especially when emergency vehicles are rushing to a destination. The cellular communication system determines the location of the emergency vehicle, and relays the location to the traffic planner. The traffic planner, in turn, controls the traffic lights to clear the traffic along the route traveled by the emergency vehicle. The cellular communication system can also determine the location of any vehicle carrying a subscriber unit and provide navigational information that helps the vehicle arrive at its destination. The navigational information includes road maps and directions.

Abstract: System for producing a plurality of semiconductor device assemblies utilizing a grid array of conductive epoxy for connecting them to an electronic system. Conductive epoxy is screen printed in a desired pattern onto a printed wire board of the semiconductor device assembly. The conductive epoxy is B-staged by heating in an oven. The semiconductor device assembly is then placed onto a system printed circuit board wherein the B-staged conductive epoxy is further cured by heat and effectively makes mechanical and electrical connections between the semiconductor device assembly and the system printed circuit board.

Abstract: In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement.

Abstract: A semiconductor device assembly having external connections, including power supply connections such as to a power source or ground, is made without resort to bond fingers. Rather, external connections are directly made from a semiconductor die to a conductive layer. The conductive layer is disposed on one surface of a printed wring board and is divided into electrically insulated conductive segments. Each of the conductive segments is connected to an external connection, and includes one or more interconnects that can be directly connected to a semiconductor die. The conductive segments are surrounded by an array of bond fingers which serve to connect the semiconductor die to further external connections, such as signal connections. The present invention is especially advantageous in the fabrication of pin grid array (PGA) and ball grid array (BGA) type integrated circuit packages.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.