Abstract: A self-timed phase detector for detecting the phase of an input signal, such as a high speed serial data stream. The self-timed phase detector includes a precharged latch, a phase detector circuit and a data valid gate. The precharged latch has a latch input, a sample clock input and first and second complementary latch outputs. The first and second complementary latch outputs have an active state and a precharged state. The phase detector circuit is coupled to the first latch output and generates a phase signal on a phase output as a function of the phase of the input signal. The data valid gate is coupled to the phase output for passing the phase signal when the latch outputs are in the active state and for blocking the phase signal when the latch outputs are in the precharged state.

Abstract: A phase locked loop includes a voltage controlled oscillator (VCO) for generating output VCO pulses. A frequency divider divides the VCO pulses by a variable number to produce frequency divided pulses whose phase is compared with that of input reference pulses by a phase detector. An update pulse is produced by the phase comparator having a pulsewidth corresponding to the detected phase difference. A pulse generator generates a train of update pulses having a combined pulsewidth equal to the pulsewidth of the update pulse, with the update pulses being substantially equally distributed within each period of the reference pulses to produce low output ripple. The update pulses are integrated by a loop filter to produce a D.C. control voltage that controls the VCO to vary the frequency of the VCO pulses such that the phase difference is adjusted toward zero. The frequency divider comprises a binary counter and a controller that enable the frequency divider to divide by a number N that is not a power of 2.

Abstract: A gate array is disclosed having a programmable polysilicon layer which serves as both the gate electrodes for MOS transistors and routing lines for some connections between gate electrodes. The gate array structure is formed on a semiconductor substrate and has an array of identical base cells located in a core region of the structure. Each such base cell includes the following elements: (1) a plurality of transistors, each of which includes a gate electrode; and (2) one or more gate connection strips formed on the substrate and electrically connecting selected gate electrodes of two or more of the transistors. Preferably, the gate connection strips are made from the same material as the selected gate electrodes (e.g., polysilicon) and are integrally connected therewith. The gate connection strips may patterned (i.e., programmed) to form substrate level routing between gates of various transistors.

Abstract: According to the present invention, there is provided a method for determining glitch power in a logic circuit having a power supply terminal, a first input, a second input, and an output coupled to a capacitive load.

Abstract: A semiconductor device package for one or more semiconductor dice having core circuits and input-output circuits uses a package substrate having one pair of biplanar conductive planes and another pair of biplanar conductive planes. The pairs of planes are positioned in a coplanar relationship between the package substrate top surface and bottom surface. The top surface has lands connected to the conductive planes and to the power bond pads for the core circuits and input-output circuits on the semiconductor die. The top surface has many top traces connected to the signal bond pads on the semiconductor die. The package substrate may have a die paddle connected to one land and/or thermal vias to conduct heat away from the semiconductor die. Power may be supplied to die core circuits through one pair of planes and to die input-output circuits through another pair of planes to decouple the core circuits from the input-output circuits and minimize noise induced false switching in either set of circuits.

Abstract: An integrated circuit structure is described having a non-metallic electrically conductive plate preferably placed over an insulating layer formed over the uppermost layer of metal lines. The electrically conductive non-metallic plate is operative to terminate electric field lines emanating from at least some of the metal lines in the metal layers under the insulating layer beneath the non-metallic electrically conductive plate, particularly the uppermost metal lines, i.e., those spaced the farthest distance from the underlying semiconductor substrate. The conductive plate may be connected to either a ground line or a power line. In another embodiment, the non-metallic electrically conductive plate may be located between at least the uppermost layer of metal lines and one or more lower layers of metal lines, with insulating layers separating the non-metallic electrically conductive plate from such metal lines.

Abstract: A semiconductor memory device capacitor is disclosed which has a trench capacitor portion provided in a semiconductor substrate and a fin capacitor portion provided above the substrate. The trench capacitor portion includes (i) a trench extending from an upper surface of the semiconductor substrate downwardly into the substrate, and (ii) an electrically conductive trench electrode provided interior to the trench. And the fin capacitor portion includes (i) a fin electrode having a body portion and two or more electrically conductive fins extending outwardly from the body portion, (ii) a fin dielectric layer conformally coating the two or more electrically conductive fins, and (iii) a cell electrode surrounding and in intimate contact with the two or more electrically conductive fins.

Abstract: A flip chip substrate includes first and second conductive layers, and a dielectric layer interposed therebetween. Each conductive layer includes a repeating pattern of a group of I/O signal traces such as two I/O signal traces, followed by a wider power or ground trace. The I/O traces on one conductive layer lie atop or below power or ground traces on the other conductive layer. The wider power and ground traces provide shielding on either side of the I/O trace group, as well as above or below.

Abstract: A microelectronic circuit includes a plurality of circuitry blocks and sub-blocks, a clock driver, an electrical interconnect that directly connects the clock driver to the sub-blocks, and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively. A method of producing a hierarchial clock distribution system for the circuit includes determining clock skews between the clock driver and the sub-blocks respectively. Delay buffers are selected from a predetermined set of delay buffers having the same physical size and different delays, with the delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively. Each delay buffer includes a delay line, and a number of loading elements that are connected to the delay line, with the number of loading elements being selected to provide the required clock delay for the respective sub-block.

Abstract: A novel synchronization scheme for use in connection with digital signal video decoder comprises a pre-parser, a channel buffer, and a post-parser. The pre-parser synchronizes to a multiplexed system bitstream received from a fixed rate channel. The video bitstream component of a multiplexed system bitstream is then extracted and synchronized prior to being transferred bit-serially from the pre-parser to a channel buffer. The post-parser is coupled to the channel buffer and to a video decoder in a series configuration. The post-parser separates the various layers of video data from the video bitstream component. The post-parser performs a translation operation on the video bitstream component and converts the bitstream data into symbol data. The symbol data is subsequently processed by the video decoder so as to reconstruct an originally encoded picture or frame.

Abstract: A process monitor for a CMOS integrated circuit includes first and second delay units that are connected in a ring to constitute a ring oscillator that generates pulses having different phases at the outputs of the delay units respectively. The delay units affect the frequency of the pulses and also the rising and falling edges of the pulses differently depending on the process factor of PMOS and NMOS transistors in the delay units. The process factor can be computed from the frequency, or the ratio of the phase differences between the rising and falling edges of the pulses at the outputs of the first and second delay units. The oscillatory configuration of the monitor is highly sensitive to variations in process factor, and enables the monitor to be embodied by a relatively small number of elements that can fit in two input/output slots in a standard integrated circuit layout.

Abstract: The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distance apart to ensure that no proximity effects will occur between elements fully integrated in different cells. An optical proximity correction technique is performed on the mask design by performing proximity correction only on those components, e.g., lines, that are not fully integrated within one cell.

Abstract: A method for filtering process gases prior to said process gases being allowed to enter a CVD chamber is provided in order to ensure high purity of the process gases. In one embodiment, the process gases are filtered with a first filter located in a first section of a gas line being isolated by valves at both ends of the gas line section. Further filtering by a second filter occurs in a downstream gas line section.

Abstract: A method of doping metal layers on integrated circuits to provide electromigration resistance and integrated circuits having metal alloy interconnects characterized by being resistant to electromigration are provided. The process consists of the steps of (1) depositing a film of a pure first conductive metal upon a semiconductor, (2) patterning and etching the deposited film, (3) subjecting the patterned conductive metal film to metallo-organic chemical vapor deposition in order to deposit upon the first deposited metal and not upon any semiconductive areas present in the patterned conductive metal film a doping amount of a second conductive metal different from the first metal, and (4) heating at a temperature sufficient to uniformly diffuse the second metal through the bulk of the patterned first conductive metal film.

Abstract: An input/output structure includes a microelectronic device connected in circuit between a contact pad and a reference potential, and a thyristor device for protecting the microelectronic device from electrostatic discharge. The thyristor device includes first and second terminals connected to the contact pad and to the reference potential respectively, a PNPN thyristor structure including a first P-region, a first N-region, a second P-region and a second N-region disposed in series between the first and second terminals, and an electrode for inducing an electric field into the second P-region. The induced electric field increases the number of charge carriers in the second P-region, and enables the device to be triggered at a lower voltage applied between the first and second terminals. The electrode includes an insulated gate, and can be connected to either the first or second terminal. The gate can include a thick field oxide layer, or a thin oxide layer to further reduce the triggering voltage.

Abstract: A large number of microelectronic circuit cells that are interconnected by a set of wiring nets are optimally placed on an integrated circuit chip such that all interconnects can be routed and the total wirelength of the interconnects is minimized. Cells are first grouped into disjoint clusters by an optimization-driven clustering technique, which uses both local and global connectivity information among the cells. This technique uses Rent's rule for combining pairs of neighboring clusters, and selects among pairs of clusters having the same Rent's exponent using distance information derived from global optimization processing. Clusters are prevented from growing to an excessive size by limiting the number of cells per cluster and the maximum area per cluster to predetermined maximum values. After the clusters are generated, they are placed using an optimization-driven placement technique, preferably "Gordian".

Abstract: The fitness of a cell placement for an integrated circuit chip is optimized by relocating at least some of cells to new locations that provide lower interconnect congestion. For each cell, the centroid of the net of cells to which the cell is connected is computed. The cell is then moved toward the centroid by a distance that is equal to the distance from the current position of the cell to the centroid multiplied by a "chaos" factor .lambda.. The value of .lambda. is selected such that the cell relocation operations will cause the placement to converge toward an optimal configuration without chaotic diversion, but with a sufficiently high chaotic element to prevent the optimization operation from becoming stuck at local fitness maxima. The new cell locations can be modified to include the effects of cells in other locations, such as by incorporating a function of cell density gradient or force direction into the computation.

Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed.

Abstract: A high-swing current mirror includes a cascode current source and a current source bias circuit. The current source includes first and second bias terminals and an output terminal. The bias circuit includes transistors M1, M2A, M2B and M3A. Transistor M1 has a gate, source, and drain, with the gate coupled to the drain. Transistor M2A has a gate, source, and drain, with the gate and source of transistor M2A coupled to the gate and source, respectively, of transistor M1. Transistor M2B has a gate and drain coupled to one another and to the second bias terminal and a source coupled to the drain of transistor M2A. Transistor M3A has a gate and drain coupled together and to the first bias terminal and a source coupled to the sources of transistors M1 and M2A. The transistors in the cascode current source and current source bias circuit have ratios of device transconductance parameters such that the cascode current source remains in saturation to provide the highest possible voltage swing at the output terminal.

Abstract: A CMOS-technology, DRAM integrated circuit includes paired P-type and N-type wells in a substrate, which wells are fabricated using a self-aligning methodology. Similarly, FET's of the DRAM circuit are fabricated in the wells of the substrate using a self-aligning methodology to provide FET's of opposite polarity in a DRAM which may have paired memory cells and dummy cells for symmetry of circuitry. The DRAM includes a multitude of capacitor structures formed atop the FET's of the substrate, and plural layers of insulative dielectric with embedded bit and word traces providing for connection of the multitude of memory cells of the DRAM to external circuitry.