Abstract: Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a command from a first bus, the command having an identification field having a value. The command is then entered into a buffer in the bridge unless another command having the same identification field value exists in the buffer. Once the command with the same identification field value is removed from the buffer, the received command is entered into the buffer. Next, the buffered command is transmitted over a second bus. A response to the command is eventually received from the second bus, the response is transmitted over the first bus, and the command is then removed from the buffer. By not entering the received command until a similar command with the same identification value is removed from the buffer, command ordering is enforced even though multiple commands are pending in the buffer.

Abstract: Inter-cell interference cancellation is provided for flash memory devices. Data from a flash memory device is processed by obtaining one or more quantized threshold voltage values for at least one target cell of the flash memory device; obtaining one or more hard decision read values for at least one aggressor cell of the target cell; determining an aggressor state of the at least one aggressor cell; determining an interference amount based on the aggressor state; determining an adjustment to the quantized threshold voltage values based on the determined interference amount; and adjusting the quantized threshold voltage values based on the determined adjustment. The quantized threshold voltage values for at least one target cell are optionally re-used from a previous soft read retry operation. The adjusted quantized threshold voltage values are optionally used to determine reliability values and are optionally applied to a soft decision decoder and/or a buffer.

Abstract: The present invention relates to an RFID system in which an RFID tag has an adjustable detection range. An RFID system according to an embodiment of the present invention includes an RFID reader receiving a signal, reading the signal, and transmitting a command signal; and an RFID tag having unique information, sensing the magnitude of the command signal received from the RFID reader, generating a voltage according to the magnitude, adjusting a tag detection range according to the generated voltage, and transmitting a response signal corresponding to the command signal to the RFID reader.

Abstract: Methods and apparatus are provided for collecting cell-level statistics for detection and decoding in flash memories. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in a page of the flash memory device; and generating cell-level statistics for the flash memory device based on a probability that a data pattern was read from the plurality of bits given that a particular pattern was written to the plurality of bits. The cell-level statistics are optionally generated substantially simultaneously with a reading of the read values, for example, as part of a read scrub process. The cell-level statistics can be used to convert the read values for the plurality of bits to a reliability value for a bit among the plurality of bits.

Abstract: Methods and apparatus are provided for detection and decoding in flash memories with error correlations for a plurality of bits within a sliding window. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and decoding the plurality of bits using a binary decoder. The non-binary log likelihood ratio captures one or more of intra-page correlations and/or intra-cell correlations. A least significant bit and a most significant bit of a given cell can be independently converted and/or jointly converted to the non-binary log likelihood ratio.

Abstract: A scan chain lockup latch comprises at least one latching element and data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal. The lockup latch is configured for coupling between first and second scan cells of a scan chain. The scan chain may be controllable between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal. The data input control circuitry may be configured to maintain the data input of the latching element at a constant logic value when the scan chain is in its functional mode of operation such that switching activity in the latching element is suppressed. The scan chain lockup latch and the associated scan chain may be implemented in scan test circuitry of an integrated circuit, for testing additional circuitry of that integrated circuit.

Abstract: Methods and systems for mapping and programming the debug logic of a circuit are provided. The system acquires a Register Transfer Level (RTL) representation of a circuit, wherein the circuit implements test logic that is externally programmable for providing one or more output signals corresponding to internal operational signals. The system analyzes the RTL representation to identify test multiplexers (MUXs) having registers for implementing the test logic, and correlates test register values for the test MUXs with outputs corresponding to the internal operational signals, based upon the RTL representation. The system further enables a user to select a desired internal operational signal for acquisition. Additionally, the system programs the test registers of the test MUXs of the circuit based on the correlated test register values to acquire the selected internal operational signal and to apply the acquired signal as one or more output signals.

Abstract: Methods and systems for backing up data of a RAID 0 volume. The system includes a plurality of storage devices implementing a logical volume in a Redundant Array of Independent Disks (RAID) level 0 configuration. The system also includes a storage controller. The storage controller is adapted to manage Input/Output (I/O) operations directed to the RAID 0 volume. The storage controller is further adapted to duplicate data stored on the RAID 0 volume to unused portions of other storage devices during an idle time of the storage controller.

Abstract: A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD.

Abstract: Systems and methods for performing timing sign-off of an integrated circuit design are disclosed. In one example embodiment the integrated circuit design is divided into plurality of blocks based on a pre-determined logic. A timing model is extracted for each block using static timing analysis (STA), wherein the extracted timing model includes timing information. An integrated circuit design level STA is performed using the extracted timing model of all of the plurality of blocks to obtain first integrated circuit design timing. The first integrated circuit timing is compared with a predetermined performance criterion.

Abstract: An analog-to-digital converter comprises a switched capacitor array configured to receive an analog input signal, a comparator having inputs coupled to respective outputs of the switched capacitor array, register circuitry having inputs coupled to respective outputs of the comparator, and a metastability detector associated with the register circuitry. The register circuitry is configured to generate control signals for application to respective control inputs of the switched capacitor array and to provide a digital output signal corresponding to the analog input signal. The metastability detector is configured to detect a metastability condition relating to signals at the respective outputs of the comparator. The register circuitry responsive to detection of the metastability condition forces bits of the digital output signal to particular logic levels.

Abstract: A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.

Abstract: A digital signal processing architecture supporting efficient coding of memory access information is provided. In an example embodiment, a digital signal processor includes an adjustment value register to store an initial adjustment value and a succeeding adjustment value. The digital signal processor may also include an address generator circuit to retrieve an instruction including a memory address value that is greater than N, and a further instruction including a further memory address value that is less than or equal to N. In addition, the digital signal processor may include a memory, which includes a high bank address space defined by memory locations that are uniquely identified with memory address values greater than N. The address generator circuit may access the high bank address space, using initial adjustment value and the memory address value, or using the succeeding adjustment value and the further memory address value.

Abstract: Methods and apparatus are provided for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns. A continuous time-decision feedback equalizer is adapted by obtaining at least one programmable signature pattern that triggers adaptation of one or more of a pole and a gain of the continuous time-decision feedback equalizer; detecting the at least one programmable signature pattern in an incoming signal; and adapting one or more of the pole and the gain of the continuous time-decision feedback equalizer when the at least one programmable signature pattern is detected in the incoming signal. The programmable signature pattern can be selected to ensure an unambiguous direction of change in an error sample when a corresponding one of the pole and the gain are modified.

Abstract: A method and storage controller for providing active-active RAID functionality within storage controller device(s). An embodiment may utilize zoning capabilities to assign a subset of physical storage devices with each storage controller. One or more storage controllers may detect that a storage controller/server has failed and may reconfigure zoning of the physical storage devices originally zoned in with the failed storage controller such that the physical storage devices of the failed zone are zoned out of the failed zone and zoned in with at least one of the remaining functional storage controllers. A reverse process may be used on recovery. An embodiment may further represent each of the physical devices zoned in with a storage controller as at least one virtual storage device and configure an additional comprehensive zone incorporating the storage controllers such that each storage controller has access to all physical storage devices through the virtual storage devices.

Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a light source, a plate, and frame. The light source can include one or more lighting elements that are in thermal communication with the light source. The plate can have a dissipative portion extending outward from a point of thermal communication between the plate and the light source. The frame can at least partially enclose the light source and may also be in thermal communication therewith.

Abstract: A redundant array of independent disks level 5 (RAID 5) with a mirroring functionality is disclosed. In one embodiment, a method for adding a mirroring functionality to a RAID 5 includes forming an array using at least three drives for storing data, creating multiple data blocks and a parity for the multiple data blocks based on the data for every (2N?1)th stripe of the array, and generating a mirror image of the multiple data blocks and the parity for the multiple data blocks for every (2N?1)th stripe to its respective 2Nth stripe of the array, where the N is an integer starting from 1.

Abstract: Provided is a shortage voltage trip device of a molded case circuit breaker. In the molded case circuit breaker, driving current applied into a trip driving part is reduced in proportion to reduction of a power applied into a circuit. When the voltage applied into the circuit is greater than a rated voltage, the trip driving part is stopped, and an operation of a trip driving mechanism is restricted by a trip lever. When the voltage applied into the circuit is less than the rated voltage, the trip driving part is operated, and the restriction of the trip driving mechanism is released by the trip lever rotated by being linked with the operation of the trip driving part. Thus, the circuit may be more simply switched, and operation reliability of a product may be improved. Also, the product may have a more simplified structure.

Abstract: A method for establishing an Ethernet communication link of a digital protective relay having at least two communication ports, includes: configuring physical layers of a first communication port and a second communication port; determining whether or not auto-negotiation with respect to the first communication port or the second communication port is successful; and replacing configuration information regarding one of physical layers of the first communication port and the second communication port with configuration information regarding the other of the physical layers of the first communication port and the second communication port according to whether or not the auto-negotiation with respect to the first communication port and the second communication port has been successful. Although Ethernet ports of the digital protective relay are connected without priority, the digital protective relay may perform the same operation.