Abstract: Disclosed is a meter capable of having communication security and a data transmitting/receiving system using the same, the system being such that a the server generates a public key and a private key corresponding to the public key, and transmits the public key to a meter, and the meter comprises a communication unit receiving the public key from a first communication unit, a frame generating unit encoding the data frame using the public key, and a controller controlling the communication unit to allow transmitting the encoded data frame.

Abstract: Provided is an apparatus for compensating offset of a current sensor detecting a motor current supplied by an inverter for PWM (Pulse Width Modulation) control of a motor, the apparatus including a current controller providing a PWM signal generated based on the motor current detected by the current sensor to the inverter, calculating an offset using the motor current detected by the current sensor in response to presence and absence of the PWM control of the motor, or offset-compensating the motor current detected by the current sensor.

Abstract: Described embodiments access data in a chained, scalable storage system. A primary agent of one or more storage devices receives a host request including a logical address from a host coupled to the primary agent. The primary agent determines, based on the logical address, a corresponding physical address in at least one of the storage devices and generates, based on the physical address, a sub-request for each determined physical address in the storage devices. The primary agent sends, via a storage device interface network operable independently of the host, the sub-requests to the storage devices. The storage device interface network is a peer-to-peer network coupling the storage devices to the primary agent. The primary agent receives sub-statuses in response to the sub-requests, and determines an overall status. The primary agent provides the overall status to the host such that the host is coupled to the storage devices without a switch.

Abstract: The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage.

Abstract: An arc extinguishing apparatus for a ring main unit includes: a housing; a plurality of fixed contactor assemblies fixed to be protruded toward the center in the housing and formed by inserting a permanent magnet for arc extinguishing by a magnetic force between a pair of main circuit fixed contacts; a plurality of earthing fixed contactors fixed to be protruded toward the center in the housing and installed to be spaced apart from the fixed contactor assemblies at a predetermined angle; a 3-phases common rotational shaft installed to be rotatable at the center of the housing; and a rotatable movable contactor assembly having a plurality of puffer guide plate sections having openings with a narrow opening width to accelerate the velocity of flow of insulating gas to extinguish arc by blowing it, and rotatable to a circuit closing position, an earthing position, and a circuit opening position.

Abstract: An auxiliary contact mechanism of a magnetic contactor includes: a contact support member having an axial recess portion formed in the center in a vertical direction; a stationary contact; a movable contact; a permanent magnet position-fixed to the contact support member and applying magnetic attractive force to restrain the movable contact so that the circuit closing position that the movable contact is in contact with the stationary contact is maintained; and a slide movable supporter having a pressing projection portion formed at a position separated apart by a predetermined distance from the movable contact when in the circuit closing position and pushing the movable contact to release the movable contact from a restrained state after a predetermined delay time has passed, when the slide movable supporter is moved downwardly upon receiving downward pressing force by the main contact slide support member.

Abstract: An apparatus includes a non-adaptive filter, an adaptive filter, and a controller. The non-adaptive filter may have non-adaptive filter coefficients and be configured to develop a non-adaptive error signal as a function of the non-adaptive filter coefficients. The adaptive filter may have adaptive filter coefficients and be configured to develop an adaptive error signal as a function of the adaptive filter coefficients. The controller may be configured to monitor a quality of the non-adaptive and adaptive error signals and perform one or more of a full coefficient update, a partial coefficient update and a fractional coefficient update of the non-adaptive filter coefficients based on a comparison of the quality of the adaptive error signal to a determined current best-attained performance measurement.

Abstract: Provided is a measuring apparatus and method of train wheel wear, the apparatus including a speed measuring unit measuring speed of a train, a position measuring unit measuring a position of the train, and a calculation unit calculating abrasiveness of a train wheel on a train based on the measured speed and position of the train, whereby status of the train wheel can be accurately learned to minimize the number of devices that may be additionally installed, and to quickly measure abrasiveness of the train wheel as well.

Abstract: Provided is a blocking filter for PLC, the blocking filter including a low pass filter unit including a capacitor and a plurality of inductors, a plurality of magnetic saturation prevention circuits each connected to the inductor in parallel to prevent magnetic saturation of the inductor, and operating in response to an interruption control signal inputted from outside, and a first switch connected or opened in response to the interruption control signal and interconnected between the low pass filter unit and a neutral line.

Abstract: Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Abstract: A multiplier circuit for generating a product of at least first and second multiplicands includes encoding circuitry comprising a plurality of encoders. Each of the encoders is operative to receive at least a subset of bits of the first multiplicand and to generate a partial product corresponding to the subset of bits of the first multiplicand. The encoding circuitry is further operative to incorporate a negation of the product as a function of at least a first control signal supplied to the multiplier circuit. The multiplier circuit further includes summation circuitry coupled with the encoding circuitry. The summation circuitry is operative to sum each of the partial products generated by the encoding circuitry to thereby generate the product without performing post-incrementation.

Abstract: Various embodiments of the present invention provide systems and methods for variable iteration data processing.

Abstract: A memory circuit includes a memory including a plurality of primary memory elements, and an error correction circuit coupled to the memory and operative to detect an error in at least one of the primary memory elements and to provide corrected data corresponding to the primary memory element. The memory circuit further includes at least one spare memory element and a control circuit operative to replace at least one of the primary memory elements with the spare memory element as a function of results generated by the error correction circuit.

Abstract: A method and apparatus generating one or more clock signals in a receiver employing decision-feedback equalization (DFE). A received signal is sampled by a data clock and a transition clock, generating a data sample signal and a transition sample signal, respectively. A DFE correction is performed by DFE circuitry on the data sample signal to generate DFE detected data bits. The transition sample signal is sliced using a weighted threshold value to generate transition data bits. One or more phase updates of the data clock and the transition clocks are in response to the DFE detected data bits and the transition data bits. The weighted threshold is calculated from at least one of the prior-received DFE detected data bits. In one embodiment, the DFE detection may also be dependent on an effective delay (?) of the DFE circuit in relation to the received signal baud-period, T.

Abstract: Disclosed is a virtual machine system where hardware timer interrupts are processed by a first virtual machine. The first virtual machine writes a timer value to a shared memory location while processing the hardware timer interrupt. The timer value may be based on a kernel timing parameter maintained by the operating system of the first virtual machine. A second virtual machine may read the shared timer value from the shared memory location in order to time inter-virtual machine processes such as I/O processing and I/O requests.

Abstract: In one embodiment, a reconfigurable cyclic shifter is selectively configurable to operate in (i) five-bit mode to cyclically shift N five-bit messages by up to N degrees or (ii) ten-bit mode to cyclically shift N ten-bit messages by up to N degrees. The reconfigurable cyclic shifter has two five-bit N/2-way non-reconfigurable cyclic shifters. The two non-reconfigurable cyclic shifters together, without additional hardware, do not perform N degrees of cyclic shifting. Thus, five-bit and ten-bit reordering hardware is provided that enables the reconfigurable cyclic shifter to perform up to N degrees of cyclic shifting in the five- and ten-bit modes, respectively. In the five-bit mode, the N five-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts N/2 of the N messages. In ten-bit mode, N/2 of the N ten-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts five of the ten bits of each ten-bit message.

Abstract: Methods and apparatus are provided for processing a signal in a read channel using an oversampled analog to digital conversion. An oversampled analog to digital conversion is performed on an analog input signal to generate a plurality of digital samples corresponding to the analog input signal for a given bit interval. A data detection algorithm can then be applied on one or more of the digital samples to obtain a detected output. The oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain.

Abstract: A method and system for reducing head related transfer function (HRTF) storage requirements for 3-D sound processing of an input sound having a specified source angle increment is provided. Interaural time difference (ITD) values are selected based directly on the source angle increment; and HRTFs for processing the input sound are stored in angle increments larger than the source angle increment.

Abstract: A contact event between a sensing device and a storage medium is detected by receiving a signal indicating a physical proximity between the sensing device and the storage medium; generating a plurality of frequency bin outputs; comparing one or more frequency bin outputs to a corresponding first level threshold to yield a corresponding comparator output; summing the comparator output with at least one prior instance of the comparator output to yield an aggregated value; comparing the aggregated value to an aggregate threshold to yield an aggregate output; and generating a contact event output if one or more of a first group of the plurality of frequency bin outputs has an associated aggregate output set to a predefined binary value and a predefined minimum number of a second group of the plurality of frequency bin outputs has an associated aggregate output set to a predefined binary value.

Abstract: A computer-readable medium, a method of conducting a video game and a gaming system. In one embodiment, the medium contains programming instructions that cause a computer processor to: (1) conduct a video game that generates events having corresponding exclusively audible prompts and (2) convey the exclusively audible prompts to specific audio channels for sound-capable gaming controllers of a gaming system.